On Wed, Apr 27, 2011 at 5:09 PM, Yingying Tian <[email protected]> wrote:
> To whom it may concern,
>
> I am trying to implement a 3 level inclusive cache hierarchy with private
> L1 and L2 caches in each core and a shared L3 cache . In the function
> 'handle_cache_insert()' in mesiCache.cpp, there is a piece of code as below:
> ------------------------------------------------------------------------
> if(oldState != MESI_INVALID && isLowestPrivate_) {
> 714 /* send evict message to upper cache */
> 715 send_evict_message(queueEntry, oldTag);
> 716 }
> ------------------------------------------------------------------------
> I believe that this part is to enforce inclusive property. However
> 'isLowestPrivate_' is true only if it is L2 cache. So do you think it is
> correct to change this part as '...&& isLastLevelCache_' ? Also, is it the
> right and the only place to enable inclusion in all cache levels?
>
> It should work but make sure that the message reaches to L2/L1 cache and
its not filtered by bus.
- Avadh
>
> Thanks,
> Yingying Tian
>
>
> On Fri, Apr 22, 2011 at 3:49 PM, Yingying Tian <[email protected]> wrote:
>
>> To whom it may concern,
>>
>> In the cache hierarchy in marss inclusive or not? I read the manual of
>> PTLsim in which it said the cache hierarchy is assumed to be inclusive.
>> While I read the code of marss and I didn't find any invalidation occured in
>> L1 and L2 caches when the L3 cache replaced certain cache line. So I want
>> to make sure if inclusive cache is implemented in marss, or I have to
>> implement inclusion myself.
>>
>>
>> Thanks,
>> Yingying
>>
>
>
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