Hi everyone,
I am working on the CPU performance study under different cache hit latencies.
In the cacheController.cpp:
if(hit) {
delay = cacheAccessLatency_;
If the CPU encounter a stall caused by write access (dependency or buffer is
full), how does the 'delay' influence the ipc.
In other word, in which part of the code the delay is added on the sim_cycle?
Thanks a lot.
Zhenyu Sun
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