To whom it may concern, I am trying to implement a 3 level inclusive cache hierarchy for a 2-core CMP. After enabling L3 cache, I noticed that L3 cache is implemented as SimpleWTCache while L1 and L2 caches are MesiCache. However, there is on inclusion related functions implemented in SimpleWTCache class. So I changed L3 cache to be MesiCache by simply modifying the following piece of code in memoryHierarchy.cpp: ==================== //SimpleWTCache::CacheController *l3 = new SimpleWTCache::CacheController(0, l3_name->buf, this, L3_CACHE); CacheController *l3 = new CacheController(0, l3_name->buf, this, L3_CACHE); // l3->set_wt_disable(true); ====================
However the simulation exited incorrectly and the log file showed "::someStructIsFull_:" I couldn't figure out what the problem was so I tried to implement inclusion functions myself. After modifying code in CacheController.* files, I ran the simulator again which exited incorrectly again. After debugging, I found out that L3 cache successfully sent out evict_msg to its upperinterconnect_, which is a mesiBus, and broadcast_cb() in mesiBus.cpp is called several times after that because pendingRequestQueue is full. However, when request event is finally successfully added as broadcast_complete_cb [shown in the following piece of code], the simulator exited without triggering broadcast_complete_cb() functions as expected. (I added a print-out statement in the very beginning of the broadcast_complete_cb() but nothing was printed out but the program exited) ==================================== ##in mesiCache.cpp, broadcast_cb() successfully add event: memoryHierarchy_->add_event(&broadcastCompleted_, BUS_BROADCASTS_DELAY, queueEntry); if(dbg) ptl_logfile<<"DEBUG: done calling brdcast_complete_cb "<<*queueEntry<<endl; ===================================== So now I have no idea what I could do to with it. Can anyone give me any suggestions? Thanks, Yingying
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