To configure heterogeneous configuration look at core/basecore.cpp file
which creates all the cores based on the configuration parameter
'-core-config'.

I am currently working on a global configuration for cache and cores and
hope will solve the issue people are having with configuring all static
parameters of simulated machine.

- Avadh

On Thu, May 5, 2011 at 8:34 PM, Jason Clemons <[email protected]> wrote:

> Actually this reply was pretty good at giving me an idea for what I am in
> for.  It won't be easy to do but hopefully we'll get something working.
>
> Thanks for the help,
>
> Jason
>
>
> Quoting DRAM Ninjas <[email protected]>:
>
>  I'm not really an expert on this, but I'd say at least for the cache
>> parameters, you can't do that as it stands now. The cacheConstants.h
>> definitions are just used all over the place. And unfortunately a lot of
>> the
>> parameters in cacheConstants.h are used as template arguments which means
>> you can't set them at runtime.
>>
>> You could write some kind of terrible hack that if you are instantiating
>> cache X, just #define all those values right before the constructor and
>> then
>> #undef them after you're done.
>>
>> I think for your first point, it's a similar situation. I think there's
>> nothing *technically* stopping you from instantiating different cores, but
>> the infrastructure for doing so is just not there, so you'd have to hack
>> around it (i.e. instead of using the parameter from the simconfig, you'll
>> have to go through and manually instantiate cores and attach them to the
>> memory hierarchy).
>>
>> I hope at least you're planning on running all 3 of these cores at the
>> same
>> clock frequency ... if not, I doubt QEMU can run heterogeneous clock
>> frequencies, which would be a big setback ...
>>
>> That answer probably didn't help at all.
>>
>> On Mon, May 2, 2011 at 7:49 PM, Jason Clemons <[email protected]> wrote:
>>
>>  Hello Everyone,
>>>
>>>
>>>
>>> I need to run marss in a heterogeneous configuration with 2 atoms cores
>>> and
>>> 1 default core.  I am unsure how to go about this.  How do I specify this
>>> to
>>> the simulator?  Also, how would I give each atom core a different L1
>>> cache
>>> size/parameters?  I have checked out the core-models branch.
>>>
>>>
>>> Thanks,
>>>
>>> Jason
>>>
>>>
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>>> [email protected]
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>>>
>>>
>>
>
>
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