On Tue, Jun 14, 2011 at 11:19 PM, <[email protected]> wrote: > Hello, > > I'm considering doing some experiments in a few months with performance > counters in a simulated environment (e.g. last level cache miss counters, > which are available in Intel processors) and wanted to get started with > the preliminaries. When these counters work, there is usually a set of > memory mapped registers that the OS/user level can access to configure the > performance monitoring unit and view the results. > > Does marss support anything like a performance monitoring unit currently? > > Currently there is no framework as such to expose these counters. As per my knowledge, the way these counters work is like, CPU expose 2 to 4 counters and user can set which event to count. These counters can be controlled using specific MSRs and you can trap all MSR read and write by modifying 'assist_rdmsr' and 'assist_wrmsr' functions in 'decode-complex.cpp'.
Every new chip has different sets of event counters and they use different values for MSRs so I think it not possible for us to support all but if you do come up with some type of framework or configurable design, please send the patch for everyone to use. Thanks, Avadh > Thanks, > > Jim Stevens > Memory Systems Research Lab > University of Maryland-College Park > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >
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