Hi,
I have a question about L2 cache miss stat. The experiment uses 2 cores and a
shared L2 cache.
I found that there are two sections of L2 cache stat. The numbers are quite
different. Can anyone point out what are the differences?
Second, in the cacheController.cpp file, the stat update statement like
SSTAT_UPDATE(cpurequest.count.hit.read.hit.hit++, kernel_req), which section of
the L2 stats are they related to? Thanks.
- Hui
-------------------------------------------------
L2 {
lat_count { (zero) }
mesi_stats { (zero) }
snooprequest { (zero) }
annul = 0; { (zero) }
latency { (zero) }
cpurequest {
stall (total 42851) {
[ 38.3% ] write (total 16395) {
[ 0.0% ] cache_port = 0; { (zero) }
[ 0.0% ] buffer_full = 0; { (zero) }
[ 38.3% ] dependency = 16395;
}
[ 61.7% ] read (total 26456) {
[ 0.0% ] cache_port = 0; { (zero) }
[ 0.0% ] buffer_full = 0; { (zero) }
[ 61.7% ] dependency = 26456;
}
}
redirects = 0; { (zero) }
count (total 203702) {
[ 28.8% ] miss (total 58675) {
[ 5.1% ] write = 10471;
[ 23.7% ] read = 48204;
}
[ 71.2% ] hit {
write (total 49458) {
[ 100% ] hit (total 49458) {
[ 0.0% ] forward = 0; { (zero) }
[ 100% ] hit = 49458;
}
}
read (total 95569) {
[ 100% ] hit (total 95569) {
[ 0.0% ] forward = 0; { (zero) }
[ 100% ] hit = 95569;
}
}
….
….
L2 { (zero) }
CPUController {
lat_count { (zero) }
mesi_stats { (zero) }
snooprequest { (zero) }
annul = 0; { (zero) }
latency { (zero) }
cpurequest {
stall (total 292205) {
[ 32.1% ] write (total 93895) {
[ 0.0% ] cache_port = 0; { (zero) }
[ 0.0% ] buffer_full = 0; { (zero) }
[ 32.1% ] dependency = 93895;
}
[ 67.9% ] read (total 198310) {
[ 0.0% ] cache_port = 0; { (zero) }
[ 0.0% ] buffer_full = 0; { (zero) }
[ 67.9% ] dependency = 198310;
}
}
redirects = 0; { (zero) }
count (total 1571261) {
[ 21.0% ] miss (total 329684) {
[ 0.0% ] write = 0; { (zero) }
[ 21.0% ] read = 329684;
}
[ 79.0% ] hit {
write { (zero) }
read (total 1241577) {
[ 100% ] hit (total 1241577) {
[ 0.0% ] forward = 0; { (zero) }
[ 100% ] hit = 1241577;
}
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