On Mon, Jun 20, 2011 at 11:13 AM, Zhaoshi Zheng <[email protected]> wrote:
> Hi, > > I'm looking at stats generated by marss and have some confusions about the > stats tree: > > 1. Node memory.CPUController has a very high miss rate about 40% while both > L1I and L1D have over 99% hit rate, what exactly does the CPUController > count? > > CPUController is just an interface between Core and Caches. This interface is implemented purely for clean design and has no real architecture use so you can ignore this. 2. Node ooocore.c0.vcpu0.dache.load.issue has an improbably high miss rate > of 99%. Such a number doesn't make much sense to me. Again, what does this > node mean? > > This counter was used in PTLsim when cache was very simple and didnt had any request management etc.. In MARSS we don't use 'dcache.*' based structures so please ignore this counter also. - Avadh > I'm simulating a machine with only one core. > > Thanks in advance. > > Best regards, > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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