I got the answer. The config folder lies in the core-models branch. I will download it. Thanks and Regards Sparsh Mittal
On Tue, Aug 23, 2011 at 8:15 AM, sparsh1 mittal1 <[email protected]>wrote: > I appreciate your detailed reply. I am only a beginner in multi-core > programming and am only learning about coherence. By reading different > replies on the list, I am trying to understand the code. > > I have one question also. I checked out marss.dramsim recently. The Marss > webpage has a page on YAML, which mentions about the default.conf file and > config folder. However, I could not find these in the downloaded code. > Please let me know, if I need to checkout something else also. > > > Thanks and Regards > Sparsh Mittal > > > > > On Tue, Aug 23, 2011 at 12:05 AM, DRAM Ninjas <[email protected]>wrote: > >> So are you asking whether the L2 should be WT or MESI? >> >> On Mon, Aug 22, 2011 at 5:22 PM, sparsh1 mittal1 <[email protected] >> > wrote: >> >>> Hello >>> >>> Thanks for timely response. >>> >>> I saw the code in memoryHierarchy.cpp: >>> void MemoryHierarchy::shared_L2_configuration() >>> { >>> memdebug("Setting up shared L2 Configuration\n"); >>> ..... >>> //using namespace Memory::SimpleWTCache; >>> using namespace Memory::MESICache; >>> ..... >>> } >>> >> >> This must be new code, I thought previously it was a SimpleWTCache .... >> >> >>> Also, one user posted this. >>> >>> *well, i think the main reason that the last level (shared) cache is a >>> wt cache is because you don't need to enforce coherence on a shared cache. >>> the bus that connects the private caches to the last level shared cache >>> provides an ordering on requests. >>> >>> i can't really speak to the inclusivity issues, but i think that's the >>> rationale for why the llc is a wt cache instead of a mesi cache .*.. >>> >> >> This was me. Let me try to clarify -- it's not so much that you don't have >> to enforce coherence, but it's more that the bus provides an ordering on all >> requests headed into the shared L2 cache, so a writethrough or a writeback >> cache at the last level should be sufficient to maintain coherence (because >> once you have an ordering, all processors will see the same value in L2 and >> so coherence is maintained). Now, granted, I'm not a cache expert so I could >> be completely off base here. >> >> Just a related note -- I believe this configuration mechanism (and the >> shared_L2_configuration() function are all going away soon because of >> Avadh's new configuration mechanism and decoupled cache/coherence code), so >> it might be worthwhile to see what the code in the core-models branch looks >> like. >> >> >>> >>> This code and the answer seem to be contradictory or something else I >>> don't know of. Please clarify whether L2 should be WT cache or MESI cache. >>> Thanks and Regards >>> Sparsh Mittal >>> >>> >>> >>> _______________________________________________ >>> http://www.marss86.org >>> Marss86-Devel mailing list >>> [email protected] >>> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >>> >>> >> >
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