I don't know whether these mails were forwarded to the list. Hope it helps others also in avoiding the mistake which I did!
On Thu, Sep 8, 2011 at 3:02 PM, sparsh1 mittal1 <[email protected]>wrote: > I am extremely sorry to take your time. > > Oh dont be. I am really glad that you are running these experiments so we make Marss a better simulator for all. Between maintaining Marss and my PhD work, I dont get much time to explore these other designs and fix bugs in Marss. So I am really glad that you are trying out new configuration stuff and finding bugs in it. Summary of my experiments: > 1. The configuration with L1 =mesi runs fine, which you pointed out > 2. The config with L1=write-through, and L1-L2 as mesi does not work > (copied below, item 1, reduced log file attached) > I looked at the configuration and logfile and the reason its not working is because the bus interconnect is designed for MESI only. So when you attached write-through caches it doesnt work because bus is waiting for snoop response from all connected controllers. And WT caches are not designed to perform snoop operations and send response back, so they ignore the request and dont respond anything. (Look for 'responseReceived' in logfile, it at the end). Due to this behavior the cores wait for cache request to complete and never make any progress. 3. The config with L1=write-through, and L1-L2 as p2p does not work (copied > below, item 2, log file has almost nothing) > In this configuration, first thing is that you used 'p2p' interconnect to attach all L1 I,D caches and L2 cache, but 'p2p' supports connecting only 2 controllers. The solution to this issue is to create a new interconnect module that allows you to send messages directly to lower cache and send response back. To develop such a module should not take too long as you are not going to buffer any request, you'll just pass the request from source to destination just like in 'p2p' interconnect. But unlike 'p2p' this interface will support multiple Upper and single Lower interconnect. I suggest you take a look at p2p interconnect design on how it passes the message from one interconnect to other. And create a new interconnect, lets call it 'p2p_multi', that allows multiple upper connections. If you have any question regarding the design or anything else, feel free to email. - Avadh If there is any mistake in my understanding please let me know. > > > > 1. qemu/qemu-system-x86_64 -m 1G -drive XYZ -simconfig twocore.cfg -loadvm > fer_freq > initing the ooomachine > -stats fer_freq.stats -logfile fer_freq.log -kill-after-run -yamlstats > fer_freq.yaml -machine *shared_l2_2core_2M_wt* > MARSSx86::Command received : -run > Completed 0 cycles, 0 commits: 0 > Hz, 0 insns/sec: rip ffffffff81013092 00007f5ffdfce9a0[vcpu 0] > thread 0: WARNING: At cycle 16385, 0 user commits: no instructions have > committed for 16385 cycles; the pipeline could be deadlocked > > qemu-system-x86_64: ptlsim/build/core/default_core/defcore.cpp:861: virtual > bool ooo::DefaultCore::runcycle(): Assertion `0' failed. > Aborted > > shared_l2_2core_2M_wt: > > description: Shared L2 Configuration > min_contexts: 2 > cores: # The order in which core is defined is used to assign > # the cores in a machine > - type: ooo > name_prefix: ooo_ > caches: > - type: l1_128K_wt > > name_prefix: L1_I_ > insts: $NUMCORES # Per core L1-I cache > option: > private: true > last_private: true > - type: l1_128K_wt > > name_prefix: L1_D_ > insts: $NUMCORES # Per core L1-D cache > option: > private: true > last_private: true > - type: l2_2M > name_prefix: L2_ > insts: 1 # Shared L2 config > memory: > - type: dram_cont > name_prefix: MEM_ > insts: 1 # Single DRAM controller > option: > latency: 100 > interconnects: > - type: p2p > # '$' sign is used to map matching instances like: > # cpu_0, L1_I_0 > connections: > - core_$: I > L1_I_$: UPPER > - core_$: D > L1_D_$: UPPER > - L2_0: LOWER > MEM_0: UPPER > - type: *mesi_bus* > connections: > - L1_I_*: LOWER > L1_D_*: LOWER > L2_0: UPPER > > > > > > 2. qemu/qemu-system-x86_64 -m 1G -drive XYZ -loadvm fer_freq > initing the ooomachine > -stats fer_freq.stats -logfile fer_freq.log -kill-after-run -yamlstats > fer_freq.yaml -machine *shared_l2_2core_2M_wt_p2p* > qemu-system-x86_64: ptlsim/build/cache/p2p.cpp:64: virtual void > Memory::P2PInterconnect::register_controller(Memory::Controller*): Assertion > `0' failed. > Aborted > > * shared_l2_2core_2M_wt_p2p*: > > description: Shared L2 Configuration > min_contexts: 2 > cores: # The order in which core is defined is used to assign > # the cores in a machine > - type: ooo > name_prefix: ooo_ > caches: > - type: l1_128K_wt > > name_prefix: L1_I_ > insts: $NUMCORES # Per core L1-I cache > option: > private: true > last_private: true > - type: l1_128K_wt > > name_prefix: L1_D_ > insts: $NUMCORES # Per core L1-D cache > option: > private: true > last_private: true > - type: l2_2M > name_prefix: L2_ > insts: 1 # Shared L2 config > memory: > - type: dram_cont > name_prefix: MEM_ > insts: 1 # Single DRAM controller > option: > latency: 100 > interconnects: > - type: p2p > # '$' sign is used to map matching instances like: > # cpu_0, L1_I_0 > connections: > - core_$: I > L1_I_$: UPPER > - core_$: D > L1_D_$: UPPER > - L2_0: LOWER > MEM_0: UPPER > - type: *p2p* > > connections: > - L1_I_*: LOWER > L1_D_*: LOWER > L2_0: UPPER > > > Thanks and Regards > Sparsh Mittal > > > > > On Thu, Sep 8, 2011 at 1:46 PM, avadh patel <[email protected]> wrote: > >> I have pushed all the changes. You can pull it and test if your shared L2 >> configuration works or not. >> >> - Avadh >> >> >> On Thu, Sep 8, 2011 at 10:33 AM, avadh patel <[email protected]> wrote: >> >>> >>> >>> On Wed, Sep 7, 2011 at 6:18 PM, sparsh1 mittal1 <[email protected] >>> > wrote: >>> >>>> Thanks. It is copied below. >>>> Please also test for case when L1 caches are all write-through (if that >>>> is possible in real processors). l2_8M is just 8M version of l2_2M >>>> >>>> >>>> >>>> shared_l2_4core: >>>> description: Shared L2 Configuration >>>> >>>> min_contexts: 4 >>>> max_contexts: 4 >>>> cores: # The order in which core is defined is used to assign >>>> # the cores in a machine >>>> >>>> - type: ooo >>>> name_prefix: ooo_ >>>> insts: $NUMCORES >>>> caches: >>>> - type: l1_64K_mesi >>>> >>>> name_prefix: L1_I_ >>>> insts: $NUMCORES # Per core L1-I cache >>>> option: >>>> private: true >>>> last_private: true >>>> - type: l1_64K_mesi >>>> >>>> name_prefix: L1_D_ >>>> insts: $NUMCORES # Per core L1-D cache >>>> option: >>>> private: true >>>> last_private: true >>>> - type: l2_8M >>>> name_prefix: L2_ >>>> insts: 1 # Shared L2 config >>>> >>>> memory: >>>> - type: dram_cont >>>> name_prefix: MEM_ >>>> insts: 1 # Single DRAM controller >>>> option: >>>> latency: 100 >>>> interconnects: >>>> - type: p2p >>>> # '$' sign is used to map matching instances like: >>>> # cpu_0, L1_I_0 >>>> >>>> connections: >>>> - core_$: I >>>> L1_I_$: UPPER >>>> - core_$: D >>>> L1_D_$: UPPER >>>> - L2_0: LOWER >>>> MEM_0: UPPER >>>> - type: mesi_bus >>>> connections: >>>> - L1_I_*: LOWER >>>> L1_D_*: LOWER >>>> L2_0: UPPER >>>> - type: p2p >>>> connections: >>>> - L2_0: LOWER >>>> >>>> MEM_0: UPPER >>>> >>>> >>> Here you have extra p2p connection between L2_0 and MEM_0. In list of p2p >>> connections above its already defined. I am running parsec benchmarks with >>> shared_l2 connection and its running just fine. I have applied some patches >>> for MOESI code but it should work on published core-models branch. Following >>> is the config I have used for shared L2: >>> >>> shared_l2: >>> description: Shared L2 Configuration >>> min_contexts: 2 >>> cores: # The order in which core is defined is used to assign >>> # the cores in a machine >>> - type: ooo >>> name_prefix: ooo_ >>> caches: >>> - type: l1_128K_mesi >>> name_prefix: L1_I_ >>> insts: $NUMCORES # Per core L1-I cache >>> option: >>> private: true >>> last_private: true >>> - type: l1_128K_mesi >>> name_prefix: L1_D_ >>> insts: $NUMCORES # Per core L1-D cache >>> option: >>> private: true >>> last_private: true >>> - type: l2_2M >>> name_prefix: L2_ >>> insts: 1 # Shared L2 config >>> memory: >>> - type: dram_cont >>> name_prefix: MEM_ >>> insts: 1 # Single DRAM controller >>> option: >>> latency: 12 >>> interconnects: >>> - type: p2p >>> # '$' sign is used to map matching instances like: >>> # cpu_0, L1_I_0 >>> connections: >>> - core_$: I >>> L1_I_$: UPPER >>> - core_$: D >>> L1_D_$: UPPER >>> - L2_0: LOWER >>> MEM_0: UPPER >>> - type: mesi_bus >>> connections: >>> - L1_I_*: LOWER >>> L1_D_*: LOWER >>> L2_0: UPPER >>> >>> If this configuration doesn't work for you, then let me know. I am >>> planning to publish the MOESI work on core-models branch within couple of >>> days so you can pull the changes and run your shared L2 configurations. >>> >>> - Avadh >>> >>> Thanks and Regards >>>> Sparsh Mittal >>>> >>>> >>>> >>>> >>>> On Wed, Sep 7, 2011 at 5:24 PM, avadh patel <[email protected]>wrote: >>>> >>>>> Avadh >>>> >>>> >>>> >>> >> >
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