On Tue, Sep 13, 2011 at 6:34 AM, mihai pricopi <[email protected]>wrote:
> Ok I did some tests and it seems is not working with COMMIT_WIDTH > 4 and > DISPATCH_WIDTH > 4. This means we cannot have a > 4way PTLsim core unless we > add more functional units ? Where is this limitation comming from ? > > This limit is coming from the old statistics module. It seems that now its time to completely remove old statistics module from new core designs. - Avadh > > On Tue, Sep 13, 2011 at 7:08 PM, mihai pricopi <[email protected]>wrote: > >> Hi everyone, >> >> I am trying to run spec benchmarks on 2way, 4way, 6way and 8way cores. I >> used this configuration: >> >> # vim: filetype=yaml >> >> # File: ooo_base_core.conf >> # Core - Base OOO core >> core: >> ooo_2way: # 2-way base processor >> base: ooo >> params: >> ISSUE_WIDTH: 2 >> COMMIT_WIDTH: 2 >> FETCH_WIDTH: 2 >> FRONTEND_WIDTH: 2 >> DISPATCH_WIDTH: 2 >> WRITEBACK_WIDTH: 2 >> ROB_SIZE: 64 >> LOAD_Q_SIZE: 32 >> STORE_Q_SIZE: 32 >> ITLB_SIZE: 16 >> DTLB_SIZE: 16 >> >> ooo_4way: #4-way single processor >> base: ooo_2way >> params: >> ISSUE_WIDTH: 4 >> COMMIT_WIDTH: 4 >> FETCH_WIDTH: 4 >> FRONTEND_WIDTH: 4 >> DISPATCH_WIDTH: 4 >> WRITEBACK_WIDTH: 4 >> ROB_SIZE: 128 >> LOAD_Q_SIZE: 64 >> STORE_Q_SIZE: 64 >> ITLB_SIZE: 32 >> DTLB_SIZE: 32 >> >> ooo_6way: #6-way single processor >> base: ooo_4way >> params: >> ISSUE_WIDTH: 6 >> COMMIT_WIDTH: 6 >> FETCH_WIDTH: 6 >> FRONTEND_WIDTH: 6 >> DISPATCH_WIDTH: 6 >> WRITEBACK_WIDTH: 6 >> ROB_SIZE: 192 >> LOAD_Q_SIZE: 96 >> STORE_Q_SIZE: 96 >> ITLB_SIZE: 48 >> DTLB_SIZE: 48 >> >> ooo_8way: #8-way single processor >> base: ooo_6way >> params: >> ISSUE_WIDTH: 8 >> COMMIT_WIDTH: 8 >> FETCH_WIDTH: 8 >> FRONTEND_WIDTH: 8 >> DISPATCH_WIDTH: 8 >> WRITEBACK_WIDTH: 8 >> ROB_SIZE: 256 >> LOAD_Q_SIZE: 128 >> STORE_Q_SIZE: 128 >> ITLB_SIZE: 64 >> DTLB_SIZE: 64 >> >> I use create_checkpoints.py and run_bench.py scripts. The run_bench.py >> script works fine with 2way and 4way configuration when I move to 6way or >> 8way configurations I get this error message: >> >> qemu-system-x86_64: Error -5 while activating snapshot 'hmm' on 'ide0-hd0' >> Completed 0 cycles, 0 commits: 0 Hz, >> 0 insns/sec: rip 00000000fffffff0qemu-system-x86_64: >> ptlsim/build/core/default_core/defcore-pipe.cpp:1495: int >> ooo_6way::ThreadContext::dispatch(): Assertion `core.dispatchcount < >> lengthof((*(((OutOfOrderCoreStats*)&stats->ooocore.c0) + >> (coreid))).dispatch.width)' failed. >> >> >> Is seems that I don't set the size of a internal component correctly. Do >> you have any idea what's going on ? >> >> Thanks >> > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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