Hello This regards to a previous discussion (copied below): 1. So can we say that for multi-core, L1 cache can be only mesi, as per code existing now. 2. If I think of implementing p2p_multi, would you give some hint: which files/code sections would be affected (some hints you have already given below). Any precaution?
Summary of my experiments: > 1. The configuration with L1 =mesi runs fine, which you pointed out > 2. The config with L1=write-through, and L1-L2 as mesi does not work > (copied below, item 1, reduced log file attached) > I looked at the configuration and logfile and the reason its not working is because the bus interconnect is designed for MESI only. So when you attached write-through caches it doesnt work because bus is waiting for snoop response from all connected controllers. And WT caches are not designed to perform snoop operations and send response back, so they ignore the request and dont respond anything. (Look for 'responseReceived' in logfile, it at the end). Due to this behavior the cores wait for cache request to complete and never make any progress. 3. The config with L1=write-through, and L1-L2 as p2p does not work (copied > below, item 2, log file has almost nothing) > In this configuration, first thing is that you used 'p2p' interconnect to attach all L1 I,D caches and L2 cache, but 'p2p' supports connecting only 2 controllers. The solution to this issue is to create a new interconnect module that allows you to send messages directly to lower cache and send response back. To develop such a module should not take too long as you are not going to buffer any request, you'll just pass the request from source to destination just like in 'p2p' interconnect. But unlike 'p2p' this interface will support multiple Upper and single Lower interconnect. I suggest you take a look at p2p interconnect design on how it passes the message from one interconnect to other. And create a new interconnect, lets call it 'p2p_multi', that allows multiple upper connections. Thanks and Regards Sparsh Mittal
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