I believe this is the result of how QEMU allocates simulated physical memory. It puts a hole between 3.5GB and 4.0GB and moves the missing 500MB above 4.0GB in order to accomodate memory mapped IO (or else something that I don't understand) into that hole.
In other words, for a 4GB memory system, the usable space would be 0-3.5GB and 4.0GB-4.5GB. I believe what we do in DRAMSim is just to subtract off the hole to properly map the request to the proper place. On Sun, Oct 23, 2011 at 4:54 PM, sparsh mittal <[email protected]>wrote: > Hello > Here is the result of printing in logic.h, the class is AssociativeArray: > V* probe(T addr) > { > float addrInGB = (float)addr/(float)(1024*1024*1024); > if (isL2 ) > { > > std::cout<<" addr = "<<addr<<" addr in GB "<<addrInGB<<"GB "<<"\n"; > } > > ..... > } > > I have added isL2 variable, to print the addresses for only L2 cache. > > addr = 16785400 addr in GB 0.0156326GB > * addr = 4808179704 addr in GB 4.47797GB > ............ > addr = 4808179704 addr in GB 4.47797GB* > addr = 16793584 addr in GB 0.0156402GB > ... > addr = 4808177792 addr in GB 4.47796GB > addr = 51168 addr in GB 4.76539e-05GB > addr = 16804352 addr in GB 0.0156503GB > addr = 16902064 addr in GB 0.0157413GB > > addr = 16902088 addr in GB 0.0157413GB > addr = 4824080080 addr in GB 4.49277GB > > I did -m 4G. I am compiling with c=4. > I am surprised, that the addr goes more than 4GB, although I have never > seen any error of 'address out of bounds'. > > Do you know how it is possible? > > > Thanks and Regards > Sparsh Mittal > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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