On Mon, Oct 31, 2011 at 8:00 AM, sparsh mittal <[email protected]>wrote:
> Hello > > I saw in handle_interconnect that when a message is received from upper > interconnect, we do cacheAccess. When message is received from > lower_interconnect and it has data, we do cacheInsert. > What is the purpose of cacheInsert, I don't understand. Can you explain. > > When a cache receives a message from lower interconnect it can be either of the following reasons: 1. We had a read/write miss and send that to lower cache and we got the response with data : In this case we must have a pending entry in cache's queue. If we do find a pending entry then we complete our cache miss by inserting the line into cache and also send response back to upper cache/CPU. 2. In multi-core configuration other core updated the cache line and send the message with data : In some cache coherence protocols other caches sends new updated cache line so we need to handle this scenario by updating local cache line with cache insert. This scenario should not happen with simple cache controller because its not designed to work as private-cache in multi-core configuration. 3. Snoop request from interconnect : In this case based on the interconnect type a cache can receive a snoop request. For simple cache controller we haven't implemented a snoop handling, for that we use coherent cache controllers. Hope this helps. - Avadh > > Thanks and Regards > Sparsh Mittal > > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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