On Mon, Nov 28, 2011 at 9:56 PM, Ching-Tsun Chou <[email protected]>wrote:
> I'm trying to understand how virtual memory is handled in MARSS's PTLsim > and have a series of questions: > > * Does PTLsim has its own TLB? > > Yes it does. It has single level TLB implementation in both OOO and Atom models. Look for 'dtlb' and 'itlb' structures. > * If a memory access misses TLB, how does PTLsim walk the page table? > > On a TLB miss cores generate page table addresses to load/read page table entries. It simulates 3 level page-walk. > * If the page table walk results in a page fault, what does PTLsim do? > > On a page fault, QEMU implements helper functions that set up the CPU context based on page fault type and address. Once the CPU context is set, simulation model starts execution from page fault handler code from kernel. > * In simulation mode, which of PTLsim and QEMU executes the guest OS's > page fault handler? > > Its executed in simulation mode. > I would also appreciate some pointers to where the codes for the above > tasks are located. > > Both core models have their own implementation of TLB page walk. In OOO model 'tlbwalk' function in 'ooo-exec.cpp:1782' does DTLB page walk. For ITLB 'itlbwalk' function in 'ooo-pipe.cpp:86'. Similar functions exists for Atom model also. - Avadh > Many thanks in advance! > - Ching Tsun > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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