I believe this is handled on the QEMU side indepedently of MARSS. In other words, when QEMU executes an instruction that requires a load/store, it does the memory update without the intervention of MARSS. As far as what point in the code that happens (before or after the marss execution of the load/store), I'm not sure since QEMU does the whole basic block translation/caching.
On Tue, Apr 3, 2012 at 7:09 PM, Yingying Tian <[email protected]> wrote: > To whom it may concern, > > I want to know how and when QEMU updates the RAM for the simulator when > there is a write request sent from cache. For example, when there is a > memory_op_write which is a cache miss or when there is a memory_op_update > which is an evicted dirty block from cache. Since there is no real data > handled in the cache hierarchy, I wonder when the real data is updated in > the main memory, and how the CPU gets the real data to compute? Now I know > I can use loadvirt() to fetch the real data from the QEMU's memory, I still > want to know when I can fetch the updated real data of a "write" block or > an evicted dirty block. > > Thanks, > Yingying > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
_______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
