I think I've figured this out. The DMA accesses to DRAMSim2 being generated by PCI_SSD are causing the processor to stall while the DMAs finish.
-Jim > Hi, > > My SSD simulator is now up and running under marss. We are doing some > experiments with forced swapping using fluidanimate with a 64 MB main > memory swapping to the SSD. > > Everything seems to be working nicely, but I'm seeing this message in the > log file sometimes: > > [vcpu 0] thread 0: reset thread.last_commit_at_cycle to be before > redispatch_deadlock_recovery() 159521183 > > I grepped for it and saw it is coming from > ptlsim/core/ooo-core/ooo-pipe.cpp:406, but the comments and code didn't > seem to apply to what I'm doing and I was wondering if I could get a quick > explanation of what is going on here. With the hybrid memory experiments > we had to be careful about preventing pipeline deadlock (since a DRAM > cache miss actually causes a stall). But with swapping to an SSD, the OS > should actually be setting the thread to a wait state while a swap is > serviced. Is this message appearing due to an idle state or something? > > Thanks, > > Jim Stevens > University of Maryland, College Park > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
