Thanks much, that helped a great deal. While going through the code
related to memory access, I noticed that, on a write instruction, PTLsim
appears to write straight to memory regardless of cache write mode or
whether the write was a hit in the cache. The following code makes it
look that way (important parts bolded):
assert(core.memoryHierarchy->*access_cache*(request));
assert(lsq->virtaddr > 0xfff);
if(config.checker_enabled && !ctx.kernel_mode) {
add_checker_store(lsq, uop.size);
} else {
thread.ctx.*storemask_virt*(lsq->virtaddr, lsq->data,
lsq->bytemask, uop.size);
}
Some log data I saw seems to agree, but can anyone confirm that PTLsim
writes data to memory on every write, regardless of what happens in
cache? It would be helpful to know for what I'm working on. Thanks!
Sincerely,
Addison
On 05/04/2012 12:02 AM, Paul Rosenfeld wrote:
Hi Addison,
The memory state is maintained in QEMU and marss just accesses it.
Have a look at this previous thread:
http://www.mail-archive.com/[email protected]/msg00735.html
Hopefully it has enough details to get you started.
-Paul
On Thu, May 3, 2012 at 5:30 PM, Addison Mayberry
<[email protected] <mailto:[email protected]>> wrote:
Greetings,
I am doing some work with the memory hierarchy in PTLsim, and I'm
having trouble figuring out exactly how the contents of memory are
handled in MARSS in simulation mode. Does PTLsim maintain the
contents of memory, or is it stored in QEMU internal state and
accessed via a helper function? Also, can anyone point out to me
where in the code to look for the functions that actually read /
write data in memory while in simulation mode?
Any help or tips at all would be greatly appreciated. Thanks!
Sincerely,
Addison
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