On Thu, May 17, 2012 at 9:52 PM, Paul Rosenfeld <[email protected]>wrote:
> Hello all, > > Just a quick question: I noticed here: > > > https://github.com/avadhpatel/marss/blob/master/ptlsim/cache/splitPhaseBus.cpp#L345 > > that the split phase bus will schedule a broadcast complete retry for 2 > cycles later if the entry can't broadcast. I think in the past retries were > scheduled for the next cycle -- is there some reason for the change? > > This change is made to fix a very rarely occurring bug when cache controllers are not able to receive any new entry from bus. Previously, some simulations crashed at line 378 due to cache controller not available for bus to complete the broadcast. This code change simply prevents those rare crashes. 2 cycle delay was chosen as a precaution instead of 1 to not overload bus in such scenario, with assumption that it will take at-least few cycles for cache to make an entry available. - Avadh Thanks, > Paul > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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