Hi Both in boot time and when you check the cpuinfo marss was in emulation mode and it reports whatever Qemu reports. Even in the simulation mode I'm not sure if MARSS reports the configured cache information to the OS. If you just want to make sure the configuration is right yoiu can always check the log file. MARSS dump the configuration when it starts to simulate. -Furat
On Tue, Jun 19, 2012 at 7:17 AM, Muhammad Yasir Qadri <[email protected]>wrote: > Hi > Thanks Furat > Please see the attched config file. I am looking at boot time info > displayed on the QEMU terminal, also I checked cpuinfo for cache sizes > after boot. I compile this file using > > scons -Q c=16 config=config/yasir.conf > > Regards > > > > > *Yasir* > ################################## Yasir.conf > ###################################### > # vim: filetype=yaml > # > # All core and cache configuration will be in a separate file and that > will be > # included in the final config file using 'import: [filename, ...]' > > # Import files that define various core/caches > import: > - ooo_core.conf > - atom_core.conf > - l1_cache.conf > - l2_cache.conf > - moesi.conf > > memory: > dram_cont: > base: simple_dram_cont > > machine: > # Use run-time option '-machine [MACHINE_NAME]' to select > shared_l2_yasir: > description: Shared L2 Configuration > min_contexts: 2 > cores: # The order in which core is defined is used to assign > # the cores in a machine > - type: ooo > name_prefix: ooo_ > caches: > - type: l1_8K_mesi_yasir > name_prefix: L1_I_ > insts: $NUMCORES # Per core L1-I cache > option: > private: true > last_private: true > - type: l1_8K_mesi_yasir > name_prefix: L1_D_ > insts: $NUMCORES # Per core L1-D cache > option: > private: true > last_private: true > - type: l2_128K_wt_yasir > name_prefix: L2_ > insts: 1 # Shared L2 config > memory: > - type: dram_cont > name_prefix: MEM_ > insts: 1 # Single DRAM controller > option: > latency: 50 # In nano seconds > interconnects: > - type: p2p > # '$' sign is used to map matching instances like: > # cpu_0, L1_I_0 > connections: > - core_$: I > L1_I_$: UPPER > - core_$: D > L1_D_$: UPPER > - L2_0: LOWER > MEM_0: UPPER > - type: split_bus > connections: > - L1_I_*: LOWER > L1_D_*: LOWER > L2_0: UPPER > #####################################################################33 > ------------------------------ > *From:* Furat Afram <[email protected]> > *To:* Muhammad Yasir Qadri <[email protected]> > *Cc:* "[email protected]" <[email protected]> > *Sent:* Tuesday, 19 June 2012, 15:58 > *Subject:* Re: [marss86-devel] Unable to change Cache Size > > How are you checking the cache configuration ? > Can you attach your configuration file ? > -Furat > On Tue, Jun 19, 2012 at 5:33 AM, Muhammad Yasir Qadri > <[email protected]>wrote: > > Hi > I have narrowed that down a bit. I have added a machine in default.conf. I > have cleaned and compiled qemu. Then I use > scons -Q -c > scons -Q c=16 > qemu/qemu-system-x86_64 -m 1024 -hda diskimages/splash.img -simconfig > email.cfg > > but still it is showing some default configuration of 64KB L1 and 512KB L2 > on boot. I have even tried cleaning up the default.conf with only a single > configuration. Am I doing something wrong here? > *********** email.cfg******************** > -machine ooo_2_th > -stopinsns 100m > -kill-after-run > -stats results.stats > -logfile results.log > ******************************************************** > Regards > ------------------------------ > *From:* Muhammad Yasir Qadri <[email protected]> > *To:* "[email protected]" <[email protected]> > *Sent:* Monday, 18 June 2012, 16:19 > *Subject:* [marss86-devel] Unable to change Cache Size > > Hi > I am now trying to change the L1 and L2 cache sizes to 8K and 128K > respectively but the machine now boots extremely slow and still it is > showing me 64K and 512K sizes of L1 and L2 Cache. I have not changed the > line sizes and am rebuilding the Simulator after cleaning. Please help. > Regards > *Yasir* > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > > > > >
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