Hello,
Does Marss/ptlsim correctly simulate the effects of the x86 clflush
instruction (invalidate and flush cache line)? It looks to me like it
doesn't, but I would like to confirm this; I looked through the code
and I see that ptlsim/x86/decode-complex.cpp records whether or not
the cpu supports this instruction, but I didn't find much else beyond
that. I looked through the ptlsim manual, but found nothing in there
about cache flushing. I've also been running some test programs that
use clflush, but haven't noticed its effects in my simulations (cycle
counts and number of memory writes have not increased).
Does anybody have any suggestions for where to start if I'd like to
implement this instruction myself? I searched the mailing list and
came across a few posts that seem potentially related (links below),
but I haven't spend much time with the Marss code yet. If anybody
knows what steps would be required to implement support for this
instruction, or can point me to any source files in particular, that
would be greatly appreciated. I'm hoping that there's already some
function/mechanism to evict a particular cache line, and then it's
just a matter of calling it on the right line, at the right time...
Old posts related to cache flushing, but not much help at the moment:
http://www.mail-archive.com/[email protected]/msg00658.html
http://www.mail-archive.com/[email protected]/msg00925.html
Thanks,
Peter
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