Hi,
I wrote a three level cache configuration, and run it with simple
operations such as "ls". Then I met the following error. Can anybody give some
advices?
Errors:
Completed 0 cycles, 0 commits: 0 Hz,
0 insns/sec: rip ffffffff81013092 ffffffff81013092 ffffffff81013092 fffffff
Completed 311000 cycles, 0 commits: 1548600 Hz, 0
insns/sec: rip ffffffff81013092 ffffffff81013092 ffffffff81013092 fffffff
Completed 626000 cycles, 0 commits: 1574796 Hz, 0
insns/sec: rip ffffffff81013092 ffffffff81013092 ffffffff81013092 fffffff
Completed 941000 cycles, 0 commits: 1568909 Hz, 0
insns/sec: rip ffffffff81013092 ffffffff81013092 ffffffff81013092
ffffffff81013092[vcpu 0] thread 0: WARNING: At cycle 1048577, 0 user commits:
no instructions have committed for 1048577 cycles; the pipeline could be
deadlocked
qemu-system-x86_64: ptlsim/build/core/ooo-core/ooo.cpp:870: virtual bool
ooo::OooCore::runcycle(): Assertion `0' failed.
Aborted (core dumped)
Configuration:
shared_l3_cacheline_64B:
description: Shared L3 Configuration with 64 Bytes Cacheline
#max_contexts: 2
min_contexts: 2
cores: # The order in which core is defined is used to assign
# the cores in a machine
- type: ooo
name_prefix: ooo_
caches:
- type: l1I_32K_mesi_64B
name_prefix: L1_I_
insts: $NUMCORES # Per core L1-I cache
#option:
# private: true
# last_private: false
#last_private: true
- type: l1D_32K_mesi_64B
name_prefix: L1_D_
insts: $NUMCORES # Per core L1-D cache
#option:
# private: true
# last_private: false
#last_private: true
- type: l2_256K_mesi_64B
name_prefix: L2_
insts: $NUMCORES # Per core L2 config
#option:
# private: true
# last_private: true
- type: l3_8M_mesi_64B
name_prefix: L3_
insts: 1 #shared by all cores
memory:
- type: dram_cont
name_prefix: MEM_
insts: 1 # Single DRAM controller
option:
latency: 50 # In nano seconds
interconnects:
- type: p2p
# '$' sign is used to map matching instances like:
# cpu_0, L1_I_0
connections:
- core_$: I
L1_I_$: UPPER
- core_$: D
L1_D_$: UPPER
- L1_I_$: LOWER
L2_$: UPPER
- L1_D_$: LOWER
L2_$: UPPER2
- L3_0: LOWER
MEM_0: UPPER
- type: split_bus
connections:
- L2_*: LOWER
L3_0: UPPER
_______________________________________________
http://www.marss86.org
Marss86-Devel mailing list
[email protected]
https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
