Hi,
I have a question on instruction issue timing. As I know, to issue instruction, instruction should be ready by reading its operands from physical register or bypass logic, but marss seems to issue instruction not ready. In my understand, marss check instruction ready bit in dispatch time first using find_sources() in dispatch stage, and then it wakes up the waiting instructions using broadcast () in transfer stage. However, the problem is that find_sources () sets preready bit if operands' state is not PHYS_WAITING, and doesn't capture operands' bypassing state. As a result, instruction can be issued although its operands are on bypass logic but not arrived target cluster. This seems to work fine in case that forwarding latency is 0. My question is "what happens if forwarding latency is longer then 0?". I think it could problem, but I'm not 100% certain, so i want to know my question is correct. Thanks. Hanhwi
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