Hi Ankita, Thanks for the patch. Will update the github after testing.
- Avadh On Fri, Oct 5, 2012 at 5:29 PM, Ankita (Garg) Goel <[email protected]>wrote: > Hi, > > Heres a small patch for gathering TLB statistics in the Atom core > model. Let me know if it looks ok. > > diff --git a/ptlsim/core/atom-core/atomcore.cpp > b/ptlsim/core/atom-core/atomcore.cpp > index 487dba7..dc2eb43 100644 > --- a/ptlsim/core/atom-core/atomcore.cpp > +++ b/ptlsim/core/atom-core/atomcore.cpp > @@ -1187,6 +1187,8 @@ W64 AtomOp::generate_address(TransOp& uop, bool > is_st) > > /* Access TLB */ > tlb_hit = thread->core.dtlb.probe(virtaddr, thread->threadid); > + if (tlb_hit) > + thread->st_dtlb.hits++; > > /* If access is crossing page boundires, check next page */ > int page_crossing = ((lowbits(virtaddr, 12) + (op_size - 1)) >> 12); > @@ -1196,6 +1198,8 @@ W64 AtomOp::generate_address(TransOp& uop, bool > is_st) > > /* Access TLB with next page address */ > tlb_hit2 = thread->core.dtlb.probe(virtaddr2, thread->threadid); > + if (tlb_hit2) > + thread->st_dtlb.hits++; > } > > /* If there has been an exception, treat it as TLB miss. Store the > @@ -1214,6 +1218,7 @@ W64 AtomOp::generate_address(TransOp& uop, bool > is_st) > } > > /* Its a tlb-miss, initiate page-walk */ > + thread->st_dtlb.misses++; > thread->dtlb_walk_level = thread->ctx.page_table_level_count(); > thread->dtlb_miss_addr = (exception) ? page_fault_addr : > (!tlb_hit ? virtaddr : virtaddr2); > @@ -1705,6 +1710,8 @@ AtomThread::AtomThread(AtomCore& core, W8 > threadid, Context& ctx) > , st_branch_predictions(this) > , st_dcache("dcache", this) > , st_icache("icache", this) > + , st_itlb("itlb", this) > + , st_dtlb("dtlb", this) > , st_cycles("cycles", this) > , assists("assists", this, assist_names) > , lassists("lassists", this, light_assist_names) > @@ -2023,10 +2030,12 @@ bool AtomThread::fetch_probe_itlb() > { > if(core.itlb.probe((Waddr)(fetchrip), threadid)) { > // Its a TLB hit > + st_itlb.hits++; > return true; > } > > // Its a ITLB miss - do TLB page walk > + st_itlb.misses++; > itlb_walk_level = ctx.page_table_level_count(); > itlb_walk(); > > diff --git a/ptlsim/core/atom-core/atomcore.h > b/ptlsim/core/atom-core/atomcore.h > index eb2ef58..b49a59a 100644 > --- a/ptlsim/core/atom-core/atomcore.h > +++ b/ptlsim/core/atom-core/atomcore.h > @@ -994,6 +994,20 @@ namespace ATOM_CORE_MODEL { > > cache_access st_dcache, st_icache; > > + struct tlb_access : public Statable > + { > + StatObj<W64> hits; > + StatObj<W64> misses; > + > + tlb_access(const char* name, Statable *parent) > + : Statable(name, parent) > + , hits("hits", this) > + , misses("misses", this) > + {} > + }; > + > + tlb_access st_itlb, st_dtlb; > + > StatObj<W64> st_cycles; > > StatArray<W64, ASSIST_COUNT> assists; > > > -- > Regards, > Ankita > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >
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