I just came across a discussion from last year where Paul had similar issues running multi-core configuration with the Atom core model:
http://comments.gmane.org/gmane.comp.emulators.marss86/493 However, in my case, I am able to run multi-core configuration, but not SMT. Is this a known issue ? I get a segafault as soon as the simulation mode is entered, even without any workload (just ./start_sim) in this config. On Sun, Oct 7, 2012 at 11:11 PM, Ankita (Garg) Goel <[email protected]> wrote: > Hi, > > I'm getting Segmentation Fault when simulating the Atom core model > with SMT enabled. My machine config is on the lines of ooo_2_th > machine config : > > atom_2_th: > description: Atom core with 2 threads > min_contexts: 2 > cores: > - type: atom > name_prefix: atom_ > option: > threads: 2 > caches: > - type: l1_32K_mesi > name_prefix: L1_I_ > insts: $NUMCORES # Per core L1-I cache > option: > private: true > - type: l1_32K_mesi > name_prefix: L1_D_ > insts: $NUMCORES # Per core L1-D cache > option: > private: true > - type: l2_512K > name_prefix: L2_ > insts: $NUMCORES # Private L2 config > option: > private: true > last_private: true > memory: > - type: dram_cont > name_prefix: MEM_ > insts: 1 # Single DRAM controller > interconnects: > - type: p2p > connections: > - core_$: I > L1_I_$: UPPER > - core_$: D > L1_D_$: UPPER > - L1_I_$: LOWER > L2_$: UPPER > - L1_D_$: LOWER > L2_$: UPPER2 > - type: split_bus > connections: > - L2_*: LOWER > MEM_0: UPPER > > The bt from gdb is as follows: > > #0 0x00000000005a91ff in > Memory::CoherentCache::MESILogic::complete_request (this=<optimized > out>, queueEntry=0x2cb7498, > message=...) at ptlsim/build/cache/mesiLogic.cpp:305 > #1 0x000000000058f946 in > Memory::CoherentCache::CacheController::complete_request > (this=0x2cb7230, message=..., > queueEntry=0x2cb7498) at ptlsim/build/cache/coherentCache.cpp:389 > #2 0x000000000059135c in > Memory::CoherentCache::CacheController::handle_lower_interconnect > (this=0x2cb7230, message=...) > at ptlsim/build/cache/coherentCache.cpp:233 > #3 0x00000000005915ab in > Memory::CoherentCache::CacheController::handle_interconnect_cb > (this=0x2cb7230, arg=0x2b2cd80) > at ptlsim/build/cache/coherentCache.cpp:415 > #4 0x0000000000586ca8 in > superstl::TFunctor1<Memory::Controller>::operator() (this=<optimized > out>, arg=<optimized out>) > at ptlsim/lib/superstl.h:3950 > #5 0x000000000062768b in superstl::Signal::emit (this=<optimized > out>, arg=<optimized out>) at ptlsim/build/lib/superstl.cpp:1431 > #6 0x00000000005ad984 in > Memory::P2PInterconnect::controller_request_cb (this=0x2d15000, > arg=0x2b2cd30) > at ptlsim/build/cache/p2p.cpp:85 > #7 0x00000000005817ce in > superstl::TFunctor1<Memory::Interconnect>::operator() (this=<optimized > out>, arg=<optimized out>) > at ptlsim/lib/superstl.h:3950 > #8 0x000000000062768b in superstl::Signal::emit (this=<optimized > out>, arg=<optimized out>) at ptlsim/build/lib/superstl.cpp:1431 > #9 0x00000000005834c6 in > Memory::CacheController::wait_interconnect_cb (this=0x2cd6f80, > arg=0x2cd71e8) > at ptlsim/build/cache/cacheController.cpp:694 > #10 0x0000000000586c78 in > superstl::TFunctor1<Memory::CacheController>::operator() > (this=<optimized out>, arg=<optimized out>) > at ptlsim/lib/superstl.h:3950 > #11 0x000000000062768b in superstl::Signal::emit (this=<optimized > out>, arg=<optimized out>) at ptlsim/build/lib/superstl.cpp:1431 > #12 0x00000000005a545b in execute (this=0x2b308a8) at > ptlsim/cache/memoryHierarchy.h:110 > #13 Memory::MemoryHierarchy::add_event (this=0x2b2c9f0, > signal=<optimized out>, delay=<optimized out>, arg=<optimized out>) > at ptlsim/build/cache/memoryHierarchy.cpp:312 > #14 0x00000000006a5f7c in marss_add_event (signal=<optimized out>, > delay=<optimized out>, arg=<optimized out>) > at ptlsim/build/sim/machine.cpp:816 > #15 0x0000000000586050 in > Memory::CacheController::handle_interconnect_cb (this=0x2cd6f80, > arg=0x2b2cce0) > at ptlsim/build/cache/cacheController.cpp:294 > #16 0x0000000000586ca8 in > superstl::TFunctor1<Memory::Controller>::operator() (this=<optimized > out>, arg=<optimized out>) > at ptlsim/lib/superstl.h:3950 > #17 0x000000000062768b in superstl::Signal::emit (this=<optimized > out>, arg=<optimized out>) at ptlsim/build/lib/superstl.cpp:1431 > #18 0x00000000005b080e in > Memory::SplitPhaseBus::BusInterconnect::data_broadcast_completed_cb > (this=0x2d15520, arg=0x2d15788) > at ptlsim/build/cache/splitPhaseBus.cpp:509 > #19 0x00000000005b3676 in > superstl::TFunctor1<Memory::SplitPhaseBus::BusInterconnect>::operator() > (this=<optimized out>, > arg=<optimized out>) at ptlsim/lib/superstl.h:3950 > #20 0x000000000062768b in superstl::Signal::emit (this=<optimized > out>, arg=<optimized out>) at ptlsim/build/lib/superstl.cpp:1431 > ---Type <return> to continue, or q <return> to quit--- > #21 0x00000000005a46d3 in execute (this=0x2b306b0) at > ptlsim/cache/memoryHierarchy.h:110 > #22 Memory::MemoryHierarchy::clock (this=0x2b2c9f0) at > ptlsim/build/cache/memoryHierarchy.cpp:106 > #23 0x00000000006a2673 in BaseMachine::run (this=0x129a180, > config=...) at ptlsim/build/sim/machine.cpp:356 > #24 0x00000000006b1ba3 in ptl_simulate () at ptlsim/build/sim/ptlsim.cpp:1398 > #25 0x00000000005792d2 in sim_cpu_exec () at qemu/cpu-exec.c:310 > #26 0x000000000041e079 in main_loop () at qemu/vl.c:1450 > #27 main (argc=8, argv=0x7fffffffe188, envp=<optimized out>) at qemu/vl.c:3189 > > > Any ideas on what could be going wrong ? Is this a bug or some issue > with my machine configuration ? Will greatly appreciate your help on > debugging this! Please let me know if I should provide more debug > information. > > Thanks for your help! > > -- > Regards, > Ankita -- Regards, Ankita Graduate Student Department of Computer Science University of Texas at Austin _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
