Hi, I am trying to read the content of cache lines in memory controller. I added the following lines to "handle_interconnect_cb": Context& ctx=contextof( message->request->get_coreid()); W64 data= ctx.loadvirt(message->request->get_virtual_address(),3) ;
to have the virtual address in MemoryRequest,I add virtualAddress_ as field and fill it by adding some lines to ooo-pipe.cpp and ooo-exec.cpp whenever I saw a MemoryRequest initialization. I ran the simulation for moesi_private_L2 (moesi.conf) and shared_l2 (default.conf). I got the following assertion fault: Obtained 6 stack frames. Assert ptl_stable_state == 0 failed in ptlsim/build/sim/ptlsim.cpp:1335 (uint8_t ptl_simulate()) Calling Assert Callback functions Printing stack trace: qemu/qemu-system-x86_64() [0x6d00fd] qemu/qemu-system-x86_64() [0x7398c5] qemu/qemu-system-x86_64() [0x5d3c57] qemu/qemu-system-x86_64() [0x4221cd] /lib/libc.so.6(__libc_start_main+0xfd) [0x7fc39808dc4d] qemu/qemu-system-x86_64() [0x40aaf9] Aborted Anybody know how to correctly get content of cache line? or how to fix this bug? Any help is highly appreciated. Ali Shafiee Department of Computer Science University of Utah
_______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
