I had never done this before, but even I got a compiler error when I just tried to remove the L2 component. So I am not sure how this can be done.
On Thu, Oct 18, 2012 at 10:36 PM, Alireza Haghdoost <[email protected]>wrote: > Hi Ankita > > Thanks for your prompt reply. Is it possible to have single core processor > configuration without L2 cache ? Again, I will receive compilation error > when I delete L2 cache field. > > > Thanks > Alireza > > On Thu, Oct 18, 2012 at 6:43 PM, Ankita Garg <[email protected]> wrote: > >> Hi Alireza, >> >> To change the cache size, you have to add the definition of L2_1M inside >> the file config/l2_cache.conf. There you will find the definition of L2_2M >> as well. >> >> Hope that helps. >> >> Regards, >> Ankita >> >> On Thu, Oct 18, 2012 at 6:31 PM, Alireza Haghdoost >> <[email protected]>wrote: >> >>> Hi >>> >>> I am trying to change the cache size in default.conf but after every >>> change I will receive scons compilation error, for example with this config >>> : >>> machine: >>> # Use run-time option '-machine [MACHINE_NAME]' to select >>> small: >>> description: Single Core configuration >>> min_contexts: 1 >>> max_contexts: 1 >>> cores: # The order in which core is defined is used to assign >>> # the cores in a machine >>> - type: ooo >>> name_prefix: ooo_ >>> option: >>> threads: 1 >>> caches: >>> - type: l1_128K >>> name_prefix: L1_I_ >>> insts: $NUMCORES # Per core L1-I cache >>> - type: l1_128K >>> name_prefix: L1_D_ >>> insts: $NUMCORES # Per core L1-D cache >>> - type: l2_1M >>> name_prefix: L2_ >>> insts: 1 # Shared L2 config >>> memory: >>> - type: dram_cont >>> name_prefix: MEM_ >>> insts: 1 # Single DRAM controller >>> option: >>> latency: 50 # In nano seconds >>> interconnects: >>> - type: p2p >>> # '$' sign is used to map matching instances like: >>> # core_0, L1_I_0 >>> connections: >>> - core_$: I >>> L1_I_$: UPPER >>> >>> >>> >>> I will receive following compilation error : >>> >>> marss/ptlsim/tools/config_gen.py", line 591, in gen_handle_cpuid_fn >>> cfg = config["cache"][cache["type"]] >>> KeyError: 'l2_1M' >>> scons: *** [ptlsim/build/sim/small_gen.cpp] Error 1 >>> >>> >>> >>> If I return L2 size to L2_2M, the compilation error will go away. any >>> idea about this issue ? >>> >>> Thanks >>> Alireza >>> >>> >>> >>> >>> _______________________________________________ >>> http://www.marss86.org >>> Marss86-Devel mailing list >>> [email protected] >>> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >>> >>> >> >> >> -- >> Regards, >> Ankita >> >> >> > -- Regards, Ankita Graduate Student Department of Computer Science University of Texas at Austin
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