Thanks for the suggestions. I am also thinking that most of SPEC2006 have small
working set which is not sensitive to cache capacity as long as it is at least
4MB. I will try to see if parsec benchmark works.
Thanks,
kuniors
From: avadh patel
Date: 2012-11-14 16:13
To: kuniors
CC: [email protected]
Subject: Re: [marss86-devel] performance improvement when doubling LLC capacity
On Wed, Nov 14, 2012 at 1:16 PM, kuniors <[email protected]> wrote:
I am attaching the config files. Thanks,
kuniors
From: kuniors
Date: 2012-11-14 12:48
To: [email protected]
Subject: performance improvement when doubling LLC capacity
Hello,
I have done the following simulation with the marss codes.
I have two L2 config files, and the only difference:
a. 4MB, 8-way associative,
b. 8MB, 16-way associative.
And I configured the machine with these two cache configuration.
The simulation results of 27 SPEC2006 show that the performance improvement is
only a little (around 2%, only 3 of them improved a lot (~20%) ) when I double
the cache capacity. I think there might be something wrong for the improvement
is too small. Could you please let me know if I am doing something wrong?
Configuration looks ok. Can you check how much LLC cache access is there? Also
how much is cache access rate? You can use periodic stats to find out those
cache access rates. I suspect that if cache access rates are low for the
portion of benchmark that you are simulating then having large caches might not
affect overall performance.
- Avadh
Thanks,
kuniors
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