Hi, I am curious about the data cache access flow in the simple cache controller model. After looking at the source codes and tracing the simulator, I concluded that the CPUController module calls CacheController::access_fast_path function for each coming request from the CPU. Then, CacheController::access_fast_path probes CacheLines and updates LRU stack if the request is read and there is no dependency in the cache controller queue. In this way, I think that cache port contention is not considered. It also seems that the cache access latency is not modelled. Would you explain me what is the idea behind this procedure.
I really appreciate your help. Thanks, -- Mostafa
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