Hi,

I want to simulate a heterogeneous system consisting of 2 OOO & 2 in-order
cores, each type having a shared L2 cache among them. Also, the OOO cores
have bigger L1 caches and in-order cores have smaller L1s. The config I
have is:

  hetero:
    description: Out-of-order core with 2 threads
    min_contexts: 4
    cores:
      - type: ooo
        name_prefix: ooo_
        insts: 2
        option:
            threads: 1
      - type: atom
        name_prefix: atom_
        insts: 2
        option:
            threads: 1
    caches:
      - type: l1_128K_mesi
        name_prefix: L1_I_
        insts: 2 # Per core L1-I cache
        option:
            private: false
      - type: l1_128K_mesi
        name_prefix: L1_D_
        insts: 2 # Per core L1-D cache
        option:
            private: false
      - type: l1_32K_mesi
        name_prefix: L1_I_A_
        insts: 2 # Per core L1-I cache
        option:
            private: false
      - type: l1_32K_mesi
        name_prefix: L1_D_A_
        insts: 2 # Per core L1-I cache
        option:
            private: false
      - type: l2_2M_mesi
        name_prefix: L2_
        insts: 2 # Private L2 config
        option:
            private: false
            last_private: true
      - type: l3_4M
        name_prefix: L3_
        insts: 1
    memory:
      - type: dram_cont
        name_prefix: MEM_
        insts: 1 # Single DRAM controller
    interconnects:
      - type: p2p
        connections:
          - core_0: I
            L1_I_0: UPPER
          - core_0: D
            L1_D_0: UPPER
          - core_2: I
            L1_I_1: UPPER
          - core_2: D
            L1_D_1: UPPER
          - core_1: I
            L1_I_A_0: UPPER
          - core_1: D
            L1_D_A_0: UPPER
          - core_3: I
            L1_I_A_1: UPPER
          - core_3: D
            L1_D_A_1: UPPER
          - L1_I_0: LOWER
            L2_0: UPPER
          - L1_D_0: LOWER
            L2_0: UPPER2
          - L1_I_1: LOWER
            L2_0: UPPER
          - L1_D_1: LOWER
            L2_0: UPPER2
          - L1_I_A_0: LOWER
            L2_1: UPPER
          - L1_D_A_0: LOWER
            L2_1: UPPER2
          - L1_I_A_1: LOWER
            L2_1: UPPER
          - L1_D_A_1: LOWER
            L2_1: UPPER2
          - L3_0: LOWER
            MEM_0: UPPER
      - type: split_bus
        connections:
          - L2_0: LOWER
            L3_0: UPPER
          - L2_1: LOWER
            L3_0: UPPER2

The compilation goes fine, but I hit the following assert during simulation:

[vcpu 0] thread 0: WARNING: At cycle 1048577, 0 user commits: no
instructions have committed for 1048577 cycles; the pipeline could be
deadlocked
qemu-system-x86_64: ptlsim/build/core/ooo-core/ooo.cpp:917: bool
ooo::OooCore::runcycle(void*): Assertion `0' failed.
Aborted

Any thoughts on what mistake I might be making in the configuration above ?
Any suggestions on how I can improve it ?

Thanks for your help!

-- 
Regards,
Ankita
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