Hello,
I am evaluating marss86 for my new project. I ran a few basic (test) workloads
and everything works fine.
However, I tried to run the cint 2006 workloads, and 7 of them crashed.
A majority failed with the following error:
"ptlsim/build/core/ooo-core/ooo.cpp:1456: bool
ooo::ThreadContext::handle_exception(): Assertion `ctx.page_fault_addr != 0'
failed.
I am attaching a snippet of the debug file for this error. I noticed that
Marss86 website mentioned that most spec 2006 benchmarks are executed. But
I used the reference inputs for my initial evaluation.
Can you give some insight onto this error?
Thanks,
Jerry
Per-Cycle-Signal : ooo_1_1-run-cycle
OooCore::run():thread-commit
OooCore::run():issue
OooCore::run():dispatch
OooCore::run():fetch
OooCore::run():result check thread[0] rc[1]
[vcpu 1] thread 0: WARNING: At cycle 3539535, 2316577 user commits: 8895 cycles;
Exiting out-of-order core at 2316577 commits, 3705055 uops and 3539536 iterations (cycles)
Switching back to qemu rip: 0x8062f49 exception: -1 ex: 6 running: 1 sim_cycle: 3539536
Starting simulation at rip: [cpu 0]0x8062f49 [cpu 1]0xffffffff81037eea sim_cycle: 3539536
Starting base core toplevel loop
Ctx[0] eflags: 0x202
Ctx[1] eflags: 0x202
Finalizing from clock
Controller: core_0_cont Finalizing entry: Request{Memory Request: core[0] thread[0] address[0x00007a833018] robid[13] init-cycle[3539534] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180131] ownerRIP[0x8062f4a] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup] } idx[20] cycles[0] depends[67] waitFor[-1] annuled[0]
dcache_wakeup rob 13 uuid 4180131 rip 0x000008062f4a cache-miss SOM @ all ldb r10 tr0 ld4 = r37@int r0@int r0@int request Memory Request: core[0] thread[0] address[0x00007a833018] robid[13] init-cycle[3539534] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180131] ownerRIP[0x8062f4a] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup]
rob rob 13 uuid 4180131 rip 0x000008062f4a cache-miss SOM @ all ldb r10 tr0 ld4 = r37@int r0@int r0@int
Entry finalized..
Setting cycles left to 1 for dependent
Finalizing from clock
Controller: core_0_cont Finalizing entry: Request{Memory Request: core[0] thread[0] address[0x00007a833018] robid[15] init-cycle[3539534] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180133] ownerRIP[0x8062f4a] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup] } idx[67] cycles[0] depends[-1] waitFor[-1] annuled[0]
dcache_wakeup rob 15 uuid 4180133 rip 0x000008062f4a cache-miss EOM @ all stb r13 mem st5 = r37@int r0@int r19@int (wait rob 14 uuid 4180132) request Memory Request: core[0] thread[0] address[0x00007a833018] robid[15] init-cycle[3539534] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180133] ownerRIP[0x8062f4a] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup]
rob rob 15 uuid 4180133 rip 0x000008062f4a cache-miss EOM @ all stb r13 mem st5 = r37@int r0@int r19@int (wait rob 14 uuid 4180132)
Entry finalized..
Finalizing from clock
Controller: core_0_cont Finalizing entry: Request{Memory Request: core[0] thread[0] address[0x00007a482000] robid[5] init-cycle[3539534] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180123] ownerRIP[0x8062f49] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup] } idx[91] cycles[0] depends[119] waitFor[-1] annuled[0]
dcache_wakeup rob 5 uuid 4180123 rip 0x000008062f49 cache-miss SOM @ all st r44 mem st1 = r63@int r0@int r0@int request Memory Request: core[0] thread[0] address[0x00007a482000] robid[5] init-cycle[3539534] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180123] ownerRIP[0x8062f49] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup]
rob rob 5 uuid 4180123 rip 0x000008062f49 cache-miss SOM @ all st r44 mem st1 = r63@int r0@int r0@int
Entry finalized..
Setting cycles left to 1 for dependent
Finalizing from clock
Controller: core_0_cont Finalizing entry: Request{Memory Request: core[0] thread[0] address[0x00007a482000] robid[9] init-cycle[3539534] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180127] ownerRIP[0x8062f49] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup] } idx[119] cycles[0] depends[-1] waitFor[-1] annuled[0]
dcache_wakeup rob 9 uuid 4180127 rip 0x000008062f49 cache-miss @ all std r43 mem st2 = r63@int r0@int r118@int (wait rob 8 uuid 4180126) request Memory Request: core[0] thread[0] address[0x00007a482000] robid[9] init-cycle[3539534] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180127] ownerRIP[0x8062f49] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup]
rob rob 9 uuid 4180127 rip 0x000008062f49 cache-miss @ all std r43 mem st2 = r63@int r0@int r118@int (wait rob 8 uuid 4180126)
Entry finalized..
Executing event: Event< Signal:L1_D_0_Cache_Hit Clock:3539536 arg:0x3ceaf78>
Queue Entry: Request{Memory Request: core[0] thread[0] address[0x000078f13cc0] robid[0] init-cycle[3539534] ref-counter[2] op-type[memory_op_write] isData[1] ownerUUID[4180120] ownerRIP[0x8062f45] History[ {+core_0_cont} {+L1_D_0} ] Signal[ ooo_0_0-dcache-wakeup] } idx[208] sender[p2p_core_L1_D_0] sendTo[p2p_core_L1_D_0] line[Cacheline: tag[0x78f13cc0] state[1] ] depends[-1] waitFor[-1] eventFlags[00000000] annuled[0] evicting[0] isSnoop[0] isShared[0] responseData[0]
Sending message: Message: sender[0x3ce4b90] origin[0] dest[0] arg:[0x3cfc010] request[Memory Request: core[0] thread[0] address[0x000078f13cc0] robid[0] init-cycle[3539534] ref-counter[2] op-type[memory_op_write] isData[1] ownerUUID[4180120] ownerRIP[0x8062f45] History[ {+core_0_cont} {+L1_D_0} ] Signal[ ooo_0_0-dcache-wakeup] ] isShared[0] hasData[1]
Received message in controller: core_0_cont
Controller: core_0_cont Finalizing entry: Request{Memory Request: core[0] thread[0] address[0x000078f13cc0] robid[0] init-cycle[3539534] ref-counter[2] op-type[memory_op_write] isData[1] ownerUUID[4180120] ownerRIP[0x8062f45] History[ {+core_0_cont} {+L1_D_0} ] Signal[ ooo_0_0-dcache-wakeup] } idx[43] cycles[-3] depends[-1] waitFor[-1] annuled[0]
Entry finalized..
Queue Entry flags: 00000000
Executing event: Event< Signal:split_bus_00_Broadcast Clock:3539536 arg:0>
BUS:: doing arbitration..
Adding event:Event< Signal:split_bus_00_Broadcast Clock:3539537 arg:0>
Per-Cycle-Signal : ooo_0_0-run-cycle
OooCore::run():thread-commit
Can't Commit ROB entry: rob 5 uuid 4180123 rip 0x000008062f49 tlb-miss SOM @ all st r44 mem st1 = r63@int r0@int r0@int because subrob: rob 12 uuid 4180130 rip 0x000008062f49 completed-all EOM @ all addd r102 rdi = r63@int r34@int (written) r0@int
cycle 3539536 rob entry rob 13 uuid 4180131 rip 0x000008062f4a tlb-miss SOM @ all ldb r10 tr0 ld4 = r37@int r0@int r0@int tlb_walk_level: 2 virtaddr: 0xcce106dd
Init Memory Request: core[0] thread[0] address[0x000037a6a338] robid[13] init-cycle[3539536] ref-counter[0] op-type[memory_op_read] isData[1] ownerUUID[4180131] ownerRIP[0x8062f4a] History[ ] Signal[ ooo_0_0-dcache-wakeup]
Accessing Cache L1_D_0 : Request: Memory Request: core[0] thread[0] address[0x000037a6a338] robid[13] init-cycle[3539536] ref-counter[0] op-type[memory_op_read] isData[1] ownerUUID[4180131] ownerRIP[0x8062f4a] History[ ] Signal[ ooo_0_0-dcache-wakeup]
Message received is: Message: sender[0x3dec070] origin[0] dest[0] arg:[0] request[Memory Request: core[0] thread[0] address[0x000037a6a338] robid[13] init-cycle[3539536] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180131] ownerRIP[0x8062f4a] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup] ] isShared[0] hasData[0]
L1_D_0 Received message from upper interconnect
Adding event:Event< Signal:L1_D_0_Cache_Miss Clock:3539538 arg:0x3ce6b08>
Cache: L1_D_0 added queue entry: Request{Memory Request: core[0] thread[0] address[0x000037a6a338] robid[13] init-cycle[3539536] ref-counter[2] op-type[memory_op_read] isData[1] ownerUUID[4180131] ownerRIP[0x8062f4a] History[ {+core_0_cont} {+L1_D_0} ] Signal[ ooo_0_0-dcache-wakeup] } idx[62] sender[p2p_core_L1_D_0] sendTo[none] line[none]depends[-1] waitFor[-1] eventFlags[00000000] annuled[0] evicting[0] isSnoop[0] isShared[0] responseData[0]
Added Queue Entry: Request{Memory Request: core[0] thread[0] address[0x000037a6a338] robid[13] init-cycle[3539536] ref-counter[2] op-type[memory_op_read] isData[1] ownerUUID[4180131] ownerRIP[0x8062f4a] History[ {+core_0_cont} {+L1_D_0} ] Signal[ ooo_0_0-dcache-wakeup] } idx[6] cycles[-1] depends[-1] waitFor[-1] annuled[0]
cycle 3539536 rob entry rob 15 uuid 4180133 rip 0x000008062f4a tlb-miss EOM @ all stb r13 mem st5 = r37@int r0@int r19@int (wait rob 14 uuid 4180132) tlb_walk_level: 2 virtaddr: 0xcce106dd
Init Memory Request: core[0] thread[0] address[0x000037a6a338] robid[15] init-cycle[3539536] ref-counter[0] op-type[memory_op_read] isData[1] ownerUUID[4180133] ownerRIP[0x8062f4a] History[ ] Signal[ ooo_0_0-dcache-wakeup]
Accessing Cache L1_D_0 : Request: Memory Request: core[0] thread[0] address[0x000037a6a338] robid[15] init-cycle[3539536] ref-counter[0] op-type[memory_op_read] isData[1] ownerUUID[4180133] ownerRIP[0x8062f4a] History[ ] Signal[ ooo_0_0-dcache-wakeup]
Dependent entry is: Request{Memory Request: core[0] thread[0] address[0x000037a6a338] robid[13] init-cycle[3539536] ref-counter[2] op-type[memory_op_read] isData[1] ownerUUID[4180131] ownerRIP[0x8062f4a] History[ {+core_0_cont} {+L1_D_0} ] Signal[ ooo_0_0-dcache-wakeup] } idx[6] cycles[-1] depends[-1] waitFor[-1] annuled[0]
Added Queue Entry: Request{Memory Request: core[0] thread[0] address[0x000037a6a338] robid[15] init-cycle[3539536] ref-counter[1] op-type[memory_op_read] isData[1] ownerUUID[4180133] ownerRIP[0x8062f4a] History[ {+core_0_cont} ] Signal[ ooo_0_0-dcache-wakeup] } idx[38] cycles[-1] depends[-1] waitFor[6] annuled[0]
cycle 3539536 rob entry rob 5 uuid 4180123 rip 0x000008062f49 tlb-miss SOM @ all st r44 mem st1 = r63@int r0@int r0@int tlb_walk_level: 1 virtaddr: 0
Finalizing dtlb miss rob rob 5 uuid 4180123 rip 0x000008062f49 tlb-miss SOM @ all st r44 mem st1 = r63@int r0@int r0@int virtaddr: 0
mmu_index:1 index:0 virtaddr:0000000000000000 tlb_addr:ffffffffffffffff virtpage:0000000000000000 tlbpage:fffffffffffff000 addend:ffffffffffffffff
Trying to fill tlb for addr: 0
Fault for addr: 0
cycle 3539536 rob entry rob 9 uuid 4180127 rip 0x000008062f49 tlb-miss @ all std r43 mem st2 = r63@int r0@int r118@int (wait rob 8 uuid 4180126) tlb_walk_level: 1 virtaddr: 0
Finalizing dtlb miss rob rob 9 uuid 4180127 rip 0x000008062f49 tlb-miss @ all std r43 mem st2 = r63@int r0@int r118@int (wait rob 8 uuid 4180126) virtaddr: 0
mmu_index:1 index:0 virtaddr:0000000000000000 tlb_addr:ffffffffffffffff virtpage:0000000000000000 tlbpage:fffffffffffff000 addend:ffffffffffffffff
Trying to fill tlb for addr: 0
Fault for addr: 0
OooCore::run():issue
OooCore::run():dispatch
OooCore::run():fetch
mmu_index:1 index:205 virtaddr:00000000080cdf37 tlb_addr:00000000080cd000 virtpage:00000000080cd000 tlbpage:00000000080cd000 addend:00007fdccb5f9000
mmu_index:1 index:205 virtaddr:00000000080cdf37 tlb_addr:00000000080cd000 virtpage:00000000080cd000 tlbpage:00000000080cd000 addend:00007fdccb5f9000
mmu_index:1 index:205 virtaddr:00000000080cdf37 tlb_addr:00000000080cd000 virtpage:00000000080cd000 tlbpage:00000000080cd000 addend:00007fdccb5f9000
mmu_index:1 index:205 virtaddr:00000000080cdf37 tlb_addr:00000000080cd000 virtpage:00000000080cd000 tlbpage:00000000080cd000 addend:00007fdccb5f9000
OooCore::run():result check thread[0] rc[0]
[vcpu 0] thread 0: WARNING: At cycle 3539536, 2316577 user commits: 2 cycles;
Per-Cycle-Signal : ooo_1_1-run-cycle
OooCore::run():thread-commit
OooCore::run():issue
OooCore::run():dispatch
OooCore::run():fetch
OooCore::run():result check thread[0] rc[1]
[vcpu 1] thread 0: WARNING: At cycle 3539536, 2316577 user commits: 8896 cycles;
Executing event: Event< Signal:split_bus_00_Broadcast Clock:3539537 arg:0>
BUS:: doing arbitration..
Adding event:Event< Signal:split_bus_00_Broadcast Clock:3539538 arg:0>
Per-Cycle-Signal : ooo_0_0-run-cycle
OooCore::run():thread-commit
Committing ROB entry: rob 5 uuid 4180123 rip 0x000008062f49 ready-to-commit SOM @ all st r44 mem st1 = r63@int r0@int r0@int destreg_value:0000000600000005 destflags: 0002 flagmask: 0000
ROB Commit failed because Exception 5
OooCore::run():issue
OooCore::run():dispatch
OooCore::run():fetch
mmu_index:1 index:205 virtaddr:00000000080cdf37 tlb_addr:00000000080cd000 virtpage:00000000080cd000 tlbpage:00000000080cd000 addend:00007fdccb5f9000
mmu_index:1 index:205 virtaddr:00000000080cdf37 tlb_addr:00000000080cd000 virtpage:00000000080cd000 tlbpage:00000000080cd000 addend:00007fdccb5f9000
mmu_index:1 index:205 virtaddr:00000000080cdf37 tlb_addr:00000000080cd000 virtpage:00000000080cd000 tlbpage:00000000080cd000 addend:00007fdccb5f9000
mmu_index:1 index:205 virtaddr:00000000080cdf37 tlb_addr:00000000080cd000 virtpage:00000000080cd000 tlbpage:00000000080cd000 addend:00007fdccb5f9000
OooCore::run():result check thread[0] rc[2]
[vcpu 0] in exception handling at rip [0x80cdf2a mfn 0]
handle_exception, flush_pipeline.
core[0] TH[0] flush_pipeline()
realrip:000008062f49 csbase:0
[vcpu 0] Exception PageWrite called from rip 0x8062f49 at 3539537 cycles, 2231477 commits
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