Hi, The problem that you're running into is a problem with your memory hierarchy setup. Because you are using MESI for both L1 and L2, putting in the option for private and setting L2 to be last_private should fix your issue.
I'll update the webpage accordingly. Brendan On Tue, May 7, 2013 at 4:19 AM, Muhammad Yasir Qadri <[email protected]>wrote: > > > > Hi All > I have been trying to run heterogenous configuration available at > http://marss86.org/~marss86/index.php/Machine_Configuration > But I am getting the following error. Can anyone please help. > Regards > > ************************************************************************ > ERROR > ************************************************************************ > [root@Yasir marss-0.4]# qemu/qemu-system-x86_64 -m 1024 > -hda../marss/disk_images/splash.img - > simconfig email.cfg > Simulator is now waiting for a 'run' command. > PTLCALL type PTLCALL_ENQUEUE > MARSSx86::Command received : -run > Completed 0 cycles, 0 commits: 0 > Hz, 0 insns/sec Completed 248000 cycles, 0 > commits: 1236330 Hz, 0 insns/sec Completed 486000 > cycles, 0 commits: 1188883 Hz, 0 insns/sec > Completed 724000 cycles, 0 commits: 1183668 > Hz, 0 insns/sec Completed 919000 cycles, 0 > commits: 972355 Hz, 0 insns/sec: rip 0000000000400aef > ffffffff81013092 > ffffffff81013092 ffffffff81013092[vcpu 0] thread 0: WARNING: At cycle > 1048577, 0 user commits: no instructions have committed for 1048577 cycles; > the pipeline could be deadlocked > qemu-system-x86_64: ptlsim/build/core/ooo-core/ooo.cpp:876: bool ooo:: > OooCore::runcycle(void*): Assertion `0' failed. > Aborted (core dumped) > > ********************************************************************** > CONFIG FILE > ********************************************************************** > # vim: filetype=yaml > # > # All core and cache configuration will be in a separate file and that > will be > # included in the final config file using 'import: [filename, ...]' > > # Import files that define various core/caches > import: > - ooo_core.conf > - moesi.conf > cache: > l1_64k: > base: mesi_cache > params: > SIZE: 64K > LINE_SIZE: 64 # bytes > ASSOC: 8 > LATENCY: 1 > READ_PORTS: 2 > WRITE_PORTS: 1 > l2_256k: > base: mesi_cache > params: > SIZE: 256K > LINE_SIZE: 64 # bytes > ASSOC: 8 > LATENCY: 5 > READ_PORTS: 2 > WRITE_PORTS: 2 > l3_4M: > base: wb_cache > params: > SIZE: 4M > LINE_SIZE: 64 # bytes > ASSOC: 8 > LATENCY: 12 > READ_PORTS: 2 > WRITE_PORTS: 2 > > machine: > heterogeneous: > description: Mix of OOO and Atom cores with private L2 > min_contexts: 2 > cores: > - type: ooo > name_prefix: ooo_ > option: > threads: 1 > - type: atom > name_prefix: atom_ > option: > thread: 1 > caches: > - type: l1_64k > name_prefix: L1_I_ > insts: $NUMCORES > - type: l1_64k > name_prefix: L1_D_ > insts: $NUMCORES > - type: l2_256k > name_prefix: L2_ > insts: $NUMCORES > - type: l3_4M > name_prefix: L3_ > insts: 1 > memory: > - type: dram_cont > name_prefix: MEM_ > insts: 1 # Single DRAM controller > option: > latency: 12 > interconnects: > - type: p2p > connections: > - core_$: I > L1_I_$: UPPER > - core_$: D > L1_D_$: UPPER > - L1_I_$: LOWER > L2_$: UPPER > - L1_D_$: LOWER > L2_$: UPPER2 > - L3_0: LOWER > MEM_0: UPPER > - type: split_bus > connections: > - L2_*: LOWER > L3_0: UPPER > > > > > Yasir > * > * > > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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