Hi, all
Firstly thanks for providing such a good and fast full system simulator!
I'm new to this simulator and trying to figure out how to run multicore
simulation with it. However, I'm stuck on some issues recently:
1. I can successfully run the single_core configuration, use
create_checkpoints.py to create checkpoints on the disk image and then use
run_bench.py to run the benchmarks.
2. I configure the simulator for 16 ooo cores and can boot the disk image
on top of it although it was quite slow. But I can not create checkpoints
using that python scripts any more... Do you have any idea on what should I
change in that script? Also I don't quite understand what "vm_smp"
represents.
3. Is it possible to change the hardware configurations during the
benchmark running (such as dynamically changing the ROB size)?
The benchmarks I'm trying to run is PARSEC, I didn't change the
create_checkpoints.py and this is my 16-core configuration:
--------------------------------------------------------
ooo_16_core:
description: 16 out-of-order cores
min_contexts: 2
cores:
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
- type: ooo
name_prefix: ooo_
option:
threads: 1
caches:
- type: l1_128K_mesi
name_prefix: L1_I_
insts: $NUMCORES # Per core L1-I cache
option:
private: true
- type: l1_128K_mesi
name_prefix: L1_D_
insts: $NUMCORES # Per core L1-D cache
option:
private: true
- type: l2_1M_mesi
name_prefix: L2_
insts: $NUMCORES # Private L2 config
option:
private: true
last_private: true
memory:
- type: dram_cont
name_prefix: MEM_
insts: 4 # Four DRAM controllers
interconnects:
- type: p2p
connections:
- core_$: I
L1_I_$: UPPER
- core_$: D
L1_D_$: UPPER
- L1_I_$: LOWER
L2_$: UPPER
- L1_D_$: LOWER
L2_$: UPPER2
- type: split_bus
connections:
- L2_*: LOWER
MEM_0: UPPER
--------------------------------------------------------
Any help would be appreciated!!!
Thanks!!!
--Sean
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