Hi, According to the papers I have read, there should be a bus arbitrator to favor the oldest request among all of the requests chosen in each bank's request queue. However, what I see inside the DRAMSim is that the bus arbitrator follows a simple roundrobin algorithm. It starts sending the requests targeted to a certain bank (nextrank,nextbank) till it cannot find any further issuable requests to that bank. After reaching to this point, the values of nextrank and nextbank are updated to start sending the requests of the next bank on the bus. Can anyone let me know whether the new DRAM controllers do round robin or I have missunderstood the code?
Thanks in advance P.S. Here are some of my studied papers: S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D.Owens. Memory access scheduling. In ISCA-27, 2000. K. J. Nesbit, N. Aggarwal, J. Laudon, and J. E. Smith. Fair queuing memory systems. In MICRO-39, 2006
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