Hi all, I intend to simulate Intel Clovertown multi-core processor by Marssx86. Clovertown is a quad-core processor which contains two packages. in each package exists two cores and one shared L2 cache. you can find Clovertown schema at following. [image: Inline image 1] So, I wrote following machine configuration, and built Marss86 with 4 cores (scons -Q c=4):
# vim: filetype=yaml
#
# All core and cache configuration will be in a separate file and that will
be
# included in the final config file using 'import: [filename, ...]'
# Import files that define various core/caches
import:
- ooo_core.conf
- atom_core.conf
- l1_cache.conf
- l2_cache.conf
- moesi.conf
memory:
dram_cont1:
base: simple_dram_cont
machine:
# Use run-time option '-machine [MACHINE_NAME]' to select
clover_quad_mesi:
description: This configure simulates Clovertown machine which contains
two packages
min_contexts: 4
max_contexts: 4
cores: # The order in which core is defined is used to assign
# the cores in a machine
- type: ooo
name_prefix: ooo_
option:
threads: 1
caches:
- type: l1_128K_mesi
name_prefix: L1_I_
insts: $NUMCORES # Per core L1-I cache
option:
private: true
last_private: true
- type: l1_128K_mesi
name_prefix: L1_D_
insts: $NUMCORES # Per core L1-D cache
option:
private: true
last_private: true
- type: l2_2M_mesi
name_prefix: L2_
insts: 2 # Two packages
memory:
- type: dram_cont1
name_prefix: MEM_
insts: 1 # Single DRAM controller
option:
latency: 50 # In nano seconds
interconnects:
- type: p2p
# '$' sign is used to map matching instances like:
# cpu_0, L1_I_0
connections:
- core_$: I
L1_I_$: UPPER
- core_$: D
L1_D_$: UPPER
- type: split_bus
connections:
- L1_I_0: LOWER
L1_I_1: LOWER
L2_0: UPPER
- L1_I_2: LOWER
L1_I_3: LOWER
L2_1: UPPER
- L1_D_0: LOWER
L1_D_1: LOWER
L2_0: UPPER2
- L1_D_2: LOWER
L1_D_3: LOWER
L2_1: UPPER2
- L2_*: LOWER
MEM_0: UPPER
Unfortunately, I encounter with this error message:
File "/home/hamidreza/marss/ptlsim/tools/config_gen.py", line 486, in
write_interconn_logic
assert c_cfg["insts"] == "$NUMCORES"
AssertionError
scons: *** [ptlsim/build/sim/clover_quad_mesi_gen.cpp] Error 1
I set insts of L2 cache to 1, but this error didn't solve. I even set insts
of L2 cache to 4 and this error didn't solve, too. For solving the error, I
find that number of L2 instances must be directly set to "$NUMCORES". But,
I need only two L2 caches. Could you tell me how I can solve this problem?
Sorry to bother you.
--
Hamid Reza Khaleghzadeh
http://hkhaleghzadeh.webs.com
<<aa.jpg>>
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