Hello all, I intend to simulate a machine which consists of four cores and two L2 caches. Each L2 cache is shared between two cores. So, I must connect two L1 caches to one L2 cache. I made the architecture by using MESI cache and split_bus interconnection and set disable_snoop option of split_bus to true. Unfortunately, I encounter with "Segmentation fault (core dumped)" error. May I know this architecture can be simulated by MARSS86? If your answer is positive, Could you tell me how it is possible?
Thanks
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