avadh patel <avadh4all <at> gmail.com> writes: > > > On Thu, Jun 23, 2011 at 7:32 AM, kuniors <kuniors <at> gmail.com> wrote: > > > > > > > Hello, > > I am adding the detail DRAM simulation in Marss. > However, in the simulation, I got the following errors: > > > > If you are not familiar with DRAMSim project then take a look at it as its latest version uses Marss for core simulation. > > > > > [vcpu 0] thread 0: WARNING: at cycle 16385, 0 user > commits: no instructions have committed for 16385 cycles; the pipeline could be > deadlocked > qemu-qemu-system-x86_64: > ptlsim/build/core/ooocore.cpp:790: bool OutOfOrderCore::runcycle():Assertion '0' > failed. > Aborted > > First, I have tried to increase the value: sim_cycle - > thread->last_commit_at_cycle > 10*4096. It still fails. > > Then, I doubt some structuct is full. However, no > structure is full when I print out the variable. > > I checked the running procedure, at the very beginning, > the Memory::MemoryController::handle_interconnect_cb is called several times, > which I think it means there are some requests to memory. However, after several > times, this function is never called again. > > Here is my way to run Marss: > (1)scons -Q c=4 debug=1 > (2)qemu/qemu-system-x86_64 -m 4G -hda parsecROI.raw > -simconfig=configurefile > > in configurefile: > -logfile test.log > -loglevel 9 > -stats test.stats > > Can anyone give some suggestions? It is greatly > appreciated! > > > > Take a look at the logfile, it should have dump the pipeline and memory hierarchy queues to debug this issue. This mostly happens because some memory request get stuck in cache or DRAM and pipeline will wait for it. In logfile look for ROB entries to check which entry is waiting for cache miss and try to track that request in memory hierarchy. > > > - Avadh > > > > > kuniors 2011-06-23 > > _______________________________________________http://www.marss86.org > Marss86-Devel mailing listMarss86-Devel <at> cs.binghamton.eduhttps://www.cs.binghamton.edu/mailman/listinfo/marss86- devel > > > > > > <div> > <br><div class="gmail_quote">On Thu, Jun 23, 2011 at 7:32 AM, kuniors <span dir="ltr"><<a href="mailto:kuniors <at> gmail.com">kuniors <at> gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote"> > > <div> > <div>Hello,</div> > <div> </div> > <div>I am adding the detail DRAM simulation in Marss. > However, in the simulation, I got the following errors:</div> > <div></div> > </div> > </blockquote> > <div>If you are not familiar with DRAMSim project then take a look at it as its latest version uses Marss for core simulation.</div> > <blockquote class="gmail_quote"> > > <div> > <div> </div> > <div>[vcpu 0] thread 0: WARNING: at cycle 16385, 0 user > commits: no instructions have committed for 16385 cycles; the pipeline could be > deadlocked</div> > <div>qemu-qemu-system-x86_64: > ptlsim/build/core/ooocore.cpp:790: bool OutOfOrderCore::runcycle():Assertion '0' > failed.</div> > <div>Aborted</div> > <div> </div> > <div>First, I have tried to increase the value: sim_cycle - > thread->last_commit_at_cycle > 10*4096. It still fails.</div> > <div> </div> > <div>Then, I doubt some structuct is full. However, no > structure is full when I print out the variable.</div> > <div> </div> > <div>I checked the running procedure, at the very beginning, > the Memory::MemoryController::handle_interconnect_cb is called several times, > which I think it means there are some requests to memory. However, after several > times, this function is never called again.</div> > <div> </div> > <div>Here is my way to run Marss:</div> > <div>(1)scons -Q c=4 debug=1</div> > <div>(2)qemu/qemu-system-x86_64 -m 4G -hda parsecROI.raw > -simconfig=configurefile</div> > <div> </div> > <div>in configurefile:</div> > <div>-logfile test.log</div> > <div>-loglevel 9</div> > <div>-stats test.stats</div> > <div> </div> > <div>Can anyone give some suggestions? It is greatly > appreciated!</div> > <div> </div> > </div> > </blockquote> > <div>Take a look at the logfile, it should have dump the pipeline and memory hierarchy queues to debug this issue. This mostly happens because some memory request get stuck in cache or DRAM and pipeline will wait for it. In logfile look for ROB entries to check which entry is waiting for cache miss and try to track that request in memory hierarchy.</div> > > <div><br></div> > <div>- Avadh </div> > <blockquote class="gmail_quote"> > <div> > <div> </div> > <div> > <span>kuniors</span> 2011-06-23</div> > </div> > <br>_______________________________________________<br><a href="http://www.marss86.org"; target="_blank">http://www.marss86.org</a><br> > Marss86-Devel mailing list<br><a href="mailto:Marss86-Devel <at> cs.binghamton.edu">Marss86-Devel <at> cs.binghamton.edu</a><br><a href="https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel"; target="_blank">https://www.cs.binghamton.edu/mailman/listinfo/marss86- devel</a><br><br> > </blockquote> > </div> > <br> > </div> >
Hello, I have a similar problem now. I am not using DRAMsim, but just using "qemu-system-x86_64 -m 4096" with "simconfig -machine single_core" to run an application on my own image disk. I encountered this same error and I'd like to figure out what is causing this. I checked the ROB entry as Avadh suggested. In the log file I found this line: rob 2 uuid 12141238 rip 0x0000f6f46b7d ready-to-load-all @ all ldd r42 tr1 ld2 = r129@int r0@int r0@int This load seems never successes because quite a few following entries show "wait for rob 2" And below LSQ (Load-store queue) I found : ld2 uuid 12141238 rob 2 r42 @int < Data Invalid > @0x00010999ed40 And also something like this: H 0 rfid 0 r138 state int-waiting 0xdeadbeefdeadbeef| rob 2 (uuid 12141340) refcount 3 I don't fully understand what is going on there but it seems that "deadbeef" represents some memory location that hasn't been initialized yet. Now it makes sense why that load is stuck, but I still don't know what instruction inside my application is causing this error. Do you have any idea? Thanks! SF _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
