Hi It looks like your instruction executed and ready to writeback/commit but something is blocking it. Check AtomThread::writeback(). SOM: is the first uop in an x86 instruction EOM: is the last uop in an x86 instruction if the x86 instruction has only one uop it will be marked as SOM and EOM -Furat
On Wed, Oct 30, 2013 at 10:09 AM, Shweta Shinde <[email protected]>wrote: > Hi, > > I am trying to simulate my own instruction in MARSS. > The instruction does not use any existing uops so I > also want to add support for my own uops for this instruction. > I modified qemu decoder to identify this instruction and it is working fine > without MARSS. When I added support for it in MARSS, things started > breaking. > I am able to detect my instruction in decode-complex and add a TransOp > for it. > I also added a my new uop to uopimpl.cpp. But my code does not reach this > uop implementation. > After debugging I realized that the fetch queue gets filled with the same > instruction till the assert in AtopmThread::writeback() fails. > > Core has not progressed since cycle 5611182 dumping all information > Atom-Core: 0 > Fetch Queue: > Thread: 0 stats: > Atom-Ops: > [ 0] a-op th 0 uuid 3436596 rip > 0x000000400ef4 ready-to-writeback > [nonpipe|] (0 cyc) > [ 1] a-op th 0 uuid 3436613 rip > 0x000000400ef4 ready-to-writeback > [nonpipe|] (0 cyc) > .... > [31]a-op th 0 uuid 3436625 rip > 0x000000400ef4 ready-to-writeback > [nonpipe|] (0 cyc) > > I guess I am missing out some details. I have to specify the delay for my > new uop but I dont know where MARSS does this. > I also observed in the log that each instruction has a SOM and EOM, but I > am clueless from where it is coming. > I would appreciate any help if anyone has tried this before. > > Regards, > Shweta > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >
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