Hello,
I have a question about handling cache coherency protocol.
1. As I understand MarssX86 is able to handle coherency in either
snooping(only MESI) or directory(only MOESI). Right?
2. In this code:
void MESILogic::handle_local_hit(CacheQueueEntry *queueEntry)
{
switch(oldState) {
...
case MESI_SHARED:
if(type == MEMORY_OP_WRITE) {
if(controller->is_lowest_private()) {
queueEntry->line->state = MESI_MODIFIED;
newState = MESI_MODIFIED;
queueEntry->sendTo = queueEntry->sender;
controller->send_evict_to_lower(queueEntry);
controller->wait_interconnect_cb(queueEntry);
} else {
...
This core should make sure that the other cores' copy is invalidated
and then write the data in cache. I assume this happens in
wait_interconnect_cb() (correct?)but I can not understand how. How it
broadcast the message? How this core understands that all the other
cores already invalidated their copy? is there any cb function or
reply message?
also when we send eviction to lower(send_evict_to_lower), is there any
cb to understand in higher cache that eviction is already done?
I am trying to count the number of cycles that it takes to evict lower
caches and it takes to invalidate the other cores shared data.
Thank you
Alireza
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