I was mistaken. Since L3 is shared you don't need cache coherence protocol!!!
On Mon, Mar 31, 2014 at 6:09 PM, Seyed Majid Zahedi < [email protected]> wrote: > L3 cache is shared and needs to implement a coherence protocol. > Use mesi_cache for L3. > > Seyed > > > On Mon, Mar 31, 2014 at 5:54 PM, alireza nazari <[email protected]>wrote: > >> Hello, >> >> This error is killing me! Could anybody help me please? I have run a >> benchmark(Graph500) on 1,2 and 4 cores and now I am trying to run it on 8 >> and 16 cores but it errors after 3 days and jumps out! I don't know if >> that's my config file problem or sth else. >> The error is >> Completed 10285993000 cycles, 19495859693 commits: 87446 Hz, >> 74849 insns/sec: rip ffffffff8105745f ffffffff81013091 ffffffff81013091 >> ffffffff81013091 0000000000405cb2 ffffffff81013091 ffffffff81013091 >> ffffffff81013091 ffffffff81013091 ffffffff81013091 ffffffff81013091 >> ffffffff81013091 ffffffff81013091 ffffffff81013091 ffffffff81013091 >> ffffffff81013091 >> [vcpu 0] thread 0: WARNING: At cycle 10286004263, 19495870713 user >> commits: no instructions have committed for 1048577 cycles; the pipeline >> could be deadlocked >> dump_state for core[0]: SMT common structures: >> >> the unusual lines in logfile are due to the code that I added into the >> source to collect some specific data but I dont think my code is having >> anything to do with this error. >> Any help is highly appreciated. >> >> Thank you >> Alireza >> >> >> >> _______________________________________________ >> http://www.marss86.org >> Marss86-Devel mailing list >> [email protected] >> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >> >> >
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