Hello As far as I know, Marss86 does not support any prefetchers such as next-line and stream prefetcher. So, I am writing a prefetch code on Marss86. I have faced with some implementation issues. Currently, I am using the default Xeon single core configuration. The simulated system has an out-of-order and L3 caches. My questions are as below.
First, it is implementing a prefetch request. Fortunately, I found that there is a basic code for prefetching in 'cacheController.cpp' which includes 'do_prefetch' function. So, I reused the flow issuing prefetch request. However, when creating a memory request for a prefetch, I just omit some initializing parameters such as robId and ownerRIP because I do not know the values for the prefetch request. I checked the prefetch request works well through the 'handle_interconnect_cb' method. I am just wondering there is a potential problem or not. Secondly, I saw the case that the prefetch reqeusts are limited due to the lack of free entry on a cache controller. In the cache controller, the size of entry is 128 as a default. If the size is increased, are there any predictable side effects? Additionally, I did not find the MSHR related data structure. Could you explain where is the MSHR code ?? Thanks - Jeongseob Ahn
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