Forgot to include mailing list in reply. ---------- Forwarded message ---------- From: "Jesse Elwell" <[email protected]> Date: Aug 19, 2014 11:47 AM Subject: Re: [marss86-devel] Physical addresses in marss are out of bounds To: "Hongsun An" <[email protected]> Cc:
Physical memory is not necessarily laid out from 0 to sizeof(memory). Some physical addresses can be used for things other than RAM, such as MMIO, etc. On most of the machines that I have (and I believe MARSS is the same) there is a PCI hole located from physical address 3.5GB to 4GB. That means when you give the machine 8GB of RAM only 3.5GB fits before the PCI hole, then the remaining 4.5GB come after that. So you end up with addresses larger than you expect. The same happens with the 4GB machine. However, when you run the machine with 2GB, then all the RAM fits before the PCI hole so there is no gap in addresses. If you want to look at the physical memory map to confirm that this is the issue, I have been able to find it early in dmesg output (you might be able to grep for e820). On Aug 19, 2014 11:27 AM, "Hongsun An" <[email protected]> wrote: > Hi, > > I'm using marss+dramsim with 8GB memory. > I use this command- > $mem_size=8G > ./qemu/qemu-system-x86_64 -m $mem_size -drive file=$disk_name,cache=unsafe > -simconfig $simconfig -loadvm $bench -nographic -snapshot > > To check physical address in marss, I did simulation with DRAMSim2 > DEBUG_ADDR_MAP=true option. > > Here is the part of printed messages from dramsim2 log file. > 135 == New Transaction [0x20ec2c040] (Read) Rank:1 Bank:3 Row:944 > SA:0 Col:0 > 158 == New Transaction [0x20f63b040] (Read) Rank:1 Bank:6 Row:984 > SA:0 Col:96 > 166 == New Transaction [0x1de71f880] (Read) Rank:0 Bank:7 Row:30620 > SA:7 Col:113 > 170 == New Transaction [0x1de71e2c0] (Read) Rank:0 Bank:7 Row:30620 > SA:7 Col:69 > ... > 8859040 == New Transaction [0x208f19380] (Read) Rank:0 Bank:6 Row:572 > SA:0 Col:39 > 8859041 == New Transaction [0x209433e80] (Read) Rank:1 Bank:4 Row:592 > SA:0 Col:125 > 8859043 == New Transaction [0x20876de80] (Read) Rank:1 Bank:3 Row:541 > SA:0 Col:61 > 8859045 == New Transaction [0x1718fa7c0] (Read) Rank:1 Bank:6 > Row:23651 SA:5 Col:79 > 8859047 == New Transaction [0xba84c280] (Read) Rank:0 Bank:3 Row:11937 > SA:2 Col:5 > 8859048 == New Transaction [0x106454c80] (Read) Rank:0 Bank:5 > Row:16785 SA:4 Col:25 > ... > > I think physical addresses should be 33bits because memory size is 8GB. > But some physical addresses (0x2------------) are 34bits so dramsim > address mapping is fault. > > I checked physical address from handle_interconnect_cb function at > ptlsim/cache/memoryController.cpp. > However, the result was same. > > Although there is no error/warning message from marss86 and dramsim2, I > think it is not operated normally. > > This problem also happen in 4GB simulation but not happen in 2GB. > > Is there something what i missed? > > Best regards, > Ahn > > > > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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