Dear All, I am planning to use marss86 to add one new bit to TLB (and page table entry) to simulate some feature and measure the performance. I see that PTLsim TLB doesn't have any bit related to User/supervisor (U/S) and Read/Write (R/W) bits in its structure.
Q) I need to know who (PTLsim or qemu) handles the page protection and raises the segmentation fault in case of unauthorised access of memory pages by application during simulation? Q) Where is this code? Thanks and Regards, Pradeep Kumar
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