Dear all,
I would like to ask you an explanation concerning a comment in the code
of MARSSx86 within the function
void MemoryHierarchy::annul_request(W8 coreid, W8 threadid, int robid,
W64 physaddr, bool is_icache, bool is_write)
It is said the following "Flushing of the caches is disabled currently
because we need to implement a logic where every cache will check
physaddr's cache line address with pending requests and flush them."
In order to implement the missed logic, we should check all the entries
of the queues of the Cache Controllers and remove each entry that
is_same with the annuled request or we need to invalide the cacheline
that would be accessed by the annuled request, too.
In a real system, what should be done in a real system?
Thanks beforehand,
Sotiris
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