That would cause a lot of traffic, so if that's what you're looking for, I would try it. On Nov 24, 2014 11:33 AM, "Thom Popovici" <[email protected]> wrote:
> True, but that will make the data reside in the cache. I would like to see > contention at the bus level, dram level (rank, bank, row level). I thought > by integrating dramsim2 with marss and kicking out the caches I could do > that. > > I could also try to make the l1 caches very small, lets say 64B = > cache_line_size. This might help, right? > > Thanks, > Thom > > On Mon, Nov 24, 2014 at 11:29 AM, Brendan Fitzgerald < > [email protected]> wrote: > >> Possibly, but there would have to be significant changes. >> >> An easier solution would be to make L1 perfect, which is a simconfig >> option and make the latency to L2 and main memory 0. >> >> I haven't tried this so I'm not sure what might happen. >> >> On Sun, Nov 23, 2014 at 8:40 PM, Thom Popovici <[email protected]> >> wrote: >> >>> Hi, all! I am trying to do some experiments on a full system simulator >>> that permits me to remove the caches completely from the system >>> configuration. I noticed that in MARSS you have a config file. If I do >>> not >>> mention the caches will the simulator work? >>> >>> Thanks >>> >>> >>> _______________________________________________ >>> http://www.marss86.org >>> Marss86-Devel mailing list >>> [email protected] >>> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >>> >> >> > > > -- > Thom Popovici >
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