Hello, I am trying to modify the cycles consumed by specific instructions and I have a couple of questions about changing the Marss code to reflect the change:
a. The instruction latencies listed for the Atom core in atomcore.h [https://github.com/avadhpatel/marss/blob/master/ptlsim/core/atom-core/atomcore.h#L215-L380] don't seem to match the latencies listed in the Intel Optimization Reference Manual [http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf, Section 14.4, page 506]. For instance, the Intel manual states that the FDIV instruction takes 25 to 65 cycles, whereas atomcore.h defines FDIV latency to be 6 cycles [https://github.com/avadhpatel/marss/blob/master/ptlsim/core/atom-core/atomcore.h#L320]. Am I missing something when I think that the FDIV instruction latency in Marss should be greater than 6? b. As per the Intel manual, the instruction latencies vary depending on the operands and their location (e.g. BTC latency varies between 2 and 12 based on whether the operands are registers, immediate data or memory). Instead, Marss appears to assign a single latency (not necessarily the worst-case latency) to the instructions (1 cycle for all versions of BTC). Is this intentional? Is there some other code which takes the operands types into account to determine the latency? Thanks very much! Ashay _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
