Hi all, I am a cache designer. I wonder if MARSS provides total core stall cycles caused by waiting the data write into/read from cache? Usually, the write operation is not on the critical path of cache access but read operation does. So, I want to know the actual total CPU stall cycle which resulted from cache access. Should I modify the code by myself? Thank you for your help!!
SJ _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
