Hello, As I know that x86 architecture can assure the ordering between different load instructions, so I'm quite curious about how this project achieved this.
At first, I think it might be supported by squashing a speculative load instruction while an invalidation is received. However, after I read the code of coherent cache and directory, I found that the eviction sent by cache seemed never to be received by the OoO cores. So, did I miss the critical part implementation in the cache hierarchy or there is another mechanism to achieve load-load ordering? Looking forward to your kind replies, thanks! _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
