Thanks for your reply. I know cacheController is not for coherence. The thing I want to know is that why cacheController should handle UPDATE message from lower interconnect and when UPDATE message appears from lower interconnect. As I know, cacheController only send update message to lower level cache, so update message only comes from upper interconnect. Am I missing something?
Thanks, Hanhwi 2016-04-26 21:54 GMT+09:00 Brendan Fitzgerald <[email protected]>: > cacheController is for either write back or write through caches. > coherentCache is for coherence. > > On Tue, Apr 26, 2016 at 8:47 AM, hanhwi jang <[email protected]> wrote: > >> Hi, >> >> I have several questions on cache design in cacheController.cpp. The >> current implementation handles other caches' MEMORY_OP_UPDATE messages >> (cacheController.cpp:294). In my understanding, the update message >> represents evicted cache lines or statue update requests for state >> transition to SHARED state in coherent cache design. As the cache does not >> send UPDATE message to upper level caches, to see the message the cache >> should be configured to be used multicore. However, the cache seems >> designed only for single core configuration since there is no cache >> coherence state. >> >> So why does the cache should handle an update message from lower >> interconnection network that might not enter? Is there anything I missed in >> the cache design? Also, when handling the update message why should L2 and >> L3 cache forward the message to lower-level caches >> (cacheController.cpp:323)? >> >> Thanks, >> Hanhwi >> >> _______________________________________________ >> http://www.marss86.org >> Marss86-Devel mailing list >> [email protected] >> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >> >> >
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