Dear all developers: Thank you for keeping up improving this beautiful simulator.
Can you double check if the "coherentCache.cpp" file has the following missing logic for the "cache hit" condition? I think that Line 642 (in the "cache_access_cb()" function) should be corrected like this: if(line) hit = true; // (X) (Correction) ---> if(line && is_line_valid(line)) hit = true; // (O) Here are the code lines (lnk: https://github.com/avadhpatel/marss/blob/ef656b8e237291080ae267507f4f20b31fd813cc/ptlsim/cache/coherentCache.cpp#L637): 637 if(cacheLines_->get_port(queueEntry->request)) { 638 bool hit; 639 CacheLine *line = cacheLines_->probe(queueEntry->request); 640 queueEntry->line = line; 641 642 if(line) hit = true; 643 else hit = false; I verified that a lot of "invalid" state cache lines were considered "hit." Additionally, my bug report is supported by the "access_fast_path()" function in the same file that has my suggested correct hit condition (Please refer to line 435). Here are the code lines (link: https://github.com/avadhpatel/marss/blob/ef656b8e237291080ae267507f4f20b31fd813cc/ptlsim/cache/coherentCache.cpp#L428): 428 if (request->get_type() != MEMORY_OP_WRITE) 429 line = cacheLines_->probe(request); 430 431 /* 432 * if its a write, dont do fast access as the lower 433 * level cache has to be updated 434 */ 435 if(line && is_line_valid(line) && 436 request->get_type() != MEMORY_OP_WRITE) { Thank you.
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