> Hi Saurabh, > What I concerned is, although CPU0 BSPL is 6 as you said. But CPU1 is > IDLE at time, > why those pending softcall can't be dispatched to CPU1?
The problem is that siron uses global inum to generate level1 on a particular CPU. If level1 is already pending on CPU 0, CPU 1 wouldn't fire level1 using siron() because IV_PENDING flag would be set in interrupt vector table. http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/uts/sun4/ml/interrupt.s#1555 The other problem is that CPU 0 should poke CPU 1 to do softcall processing in this case which does not happen in the current implementation. I think we are seeing some problem with e100g interrupt service routine as well. It's taking longer time than usual which creates this situation more often. Thanks, /Saurabh
